rockchip: rk3288: move configure_l2ctlr back to rk3288

The configure_l2ctlr() is used only by rk3288, do not need to
locate in sys_proto.h

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index 928e4f258bb3f6bd6ec7a4cbf287ffa09884437e..905c774c15bfe5ba47b993809bf5afee7457bc03 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -6,28 +6,6 @@
 #ifndef _ASM_ARCH_SYS_PROTO_H
 #define _ASM_ARCH_SYS_PROTO_H
 
-#ifdef CONFIG_ROCKCHIP_RK3288
-#include <asm/armv7.h>
-
-static void configure_l2ctlr(void)
-{
-       uint32_t l2ctlr;
-
-       l2ctlr = read_l2ctlr();
-       l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
-       /*
-       * Data RAM write latency: 2 cycles
-       * Data RAM read latency: 2 cycles
-       * Data RAM setup latency: 1 cycle
-       * Tag RAM write latency: 1 cycle
-       * Tag RAM read latency: 1 cycle
-       * Tag RAM setup latency: 1 cycle
-       */
-       l2ctlr |= (1 << 3 | 1 << 0);
-       write_l2ctlr(l2ctlr);
-}
-#endif /* CONFIG_ROCKCHIP_RK3288 */
 
 /* provided to defeat compiler optimisation in board_init_f() */
 void gru_dummy_function(int i);

diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 5300650e1910173f6bd125ce03b2a7807919e0de..7552472fbc4ea1d4e70b91c86d52c8ee32ab1719 100644 (file)
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -2,12 +2,34 @@
 /*
  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
  */
+#include <asm/armv7.h>
 #include <asm/io.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/grf_rk3288.h>
 
 #define GRF_BASE       0xff770000
 
+#ifdef CONFIG_SPL_BUILD
+static void configure_l2ctlr(void)
+{
+       u32 l2ctlr;
+
+       l2ctlr = read_l2ctlr();
+       l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+       /*
+        * Data RAM write latency: 2 cycles
+        * Data RAM read latency: 2 cycles
+        * Data RAM setup latency: 1 cycle
+        * Tag RAM write latency: 1 cycle
+        * Tag RAM read latency: 1 cycle
+        * Tag RAM setup latency: 1 cycle
+        */
+       l2ctlr |= (1 << 3 | 1 << 0);
+       write_l2ctlr(l2ctlr);
+}
+#endif
+
 int arch_cpu_init(void)
 {
 #ifdef CONFIG_SPL_BUILD