arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-Boot

This patch adds SPL support to the db-mv784mp-gp eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 27b38df344bbd6defdaa4bf1ae5608d42fb6adf8..47806f85dafadef081d8bc178b73db15daefb26e 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -236,6 +236,7 @@ config KIRKWOOD
 config TARGET_DB_MV784MP_GP
        bool "Support db-mv784mp-gp"
        select CPU_V7
+       select SUPPORT_SPL
 
 config TARGET_MAXBCM
        bool "Support maxbcm"

diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
index d7ef4071dd06809018a92bb23b97ba66bc1059a4..cc057925566c584d66b0dc73207f5a62523ad2f6 100644 (file)
--- a/board/Marvell/db-mv784mp-gp/kwbimage.cfg
+++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg
@@ -9,4 +9,4 @@ VERSION         1
 BOOT_FROM      spi
 
 # Binary Header (bin_hdr) with DDR3 training code
-BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068
+BINARY spl/u-boot-spl.bin 0000005b 00000068

diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 7aa216c47d49186fa67d360e4a33db1c5b01b4fc..a7f13e2132be1751eeaad5366d891ea023f72b8b 100644 (file)
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -1,2 +1,3 @@
-CONFIG_ARM=y
-CONFIG_TARGET_DB_MV784MP_GP=y
+CONFIG_SPL=y
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_DB_MV784MP_GP=y

diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index cb03e33b6e133a71f6b5d962dae32abeaf981bdf..1683a1582f4e0dd7ea4299ef8f67bfc937d54fb5 100644 (file)
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -11,6 +11,8 @@
  * High Level Configuration Options (easy to change)
  */
 #define CONFIG_ARMADA_XP               /* SOC Family Name */
+#define CONFIG_DB_784MP_GP             /* Board target name for DDR training */
+
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* disable board lowlevel_init */
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE
@@ -65,4 +67,51 @@
  */
 #include "mv-common.h"
 
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000   headers space (192KiB)
+ * 0x4000.4030                 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00   BootROM memory allocations (15KiB)
+ * 0x4007.fffc                 BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE           0x40004030
+#define CONFIG_SPL_MAX_SIZE            ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR      (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE                (16 << 10)
+
+#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SPL_BSS_START_ADDR + \
+                                        CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE     (16 << 10)
+
+#define CONFIG_SPL_STACK               (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE                (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LDSCRIPT            "arch/arm/mvebu-common/u-boot-spl.lds"
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS             0
+#define CONFIG_SPL_SPI_CS              0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS     0x20000
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_SYS_MVEBU_DDR
+#define CONFIG_SPD_EEPROM              0x4e
+
 #endif /* _CONFIG_DB_MV7846MP_GP_H */