ARM: tegra: Fix Tegra PWM parent clock

Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.

Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.

This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/

Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi
index 8932ea3afd5f44bc6a728b257a2dee04167d34ce..68ee7f316563b18c2213ac2b7b6cd04f5f4ccdfd 100644 (file)
--- a/arch/arm/dts/tegra114.dtsi
+++ b/arch/arm/dts/tegra114.dtsi
@@ -312,7 +312,7 @@
        };
 
        pwm: pwm@7000a000 {
-               compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
+               compatible = "nvidia,tegra114-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
                clocks = <&tegra_car TEGRA114_CLK_PWM>;

diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi
index f473ba28e4a645e3b588436ad9bc2b8c8b479b37..ffec9cae09d01081b7d01bdf24830a7c3ec43a0c 100644 (file)
--- a/arch/arm/dts/tegra124.dtsi
+++ b/arch/arm/dts/tegra124.dtsi
@@ -377,7 +377,7 @@
        };
 
        pwm: pwm@7000a000 {
-               compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
+               compatible = "nvidia,tegra124-pwm", "nvidia,tegra114-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
                clocks = <&tegra_car TEGRA124_CLK_PWM>;

diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index 15c2adc4170a3b528498942cc150b8723d4b0585..8ad71f590fa71121bed4ad686dd27bdba8520867 100644 (file)
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -782,7 +782,7 @@ struct periph_clk_init periph_clk_init_table[] = {
        { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-       { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+       { PERIPH_ID_PWM, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },

diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 415ba15e5ddd7b21bb941a6ec1f4fd2c5244831f..ca9549a318688737dfc16d841037b0484832c595 100644 (file)
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -1208,7 +1208,7 @@ struct periph_clk_init periph_clk_init_table[] = {
        { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-       { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+       { PERIPH_ID_PWM, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },

diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index 593622bfdcbdb63d8944be4060ae036f0ea7757d..067a9f1a2f1201fb8931c08f024a0361b1d3050a 100644 (file)
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -804,7 +804,7 @@ struct periph_clk_init periph_clk_init_table[] = {
        { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-       { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+       { PERIPH_ID_PWM, CLOCK_ID_PERIPH },
        { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },

diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 76fbfef580c71708290c43a0337e7c10ce896c19..900537afbe50831c3f6abd6c65c68495cd265fae 100644 (file)
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -1278,7 +1278,7 @@ struct periph_clk_init periph_clk_init_table[] = {
        { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-       { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+       { PERIPH_ID_PWM, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },

diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index b66211ce94028ebdf60997f675c1f7f8e205d84d..1dc9d09dba86749560bd7a9ef17798a5b9ec766d 100644 (file)
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -884,7 +884,7 @@ struct periph_clk_init periph_clk_init_table[] = {
        { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
        { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
-       { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
+       { PERIPH_ID_PWM, CLOCK_ID_PERIPH },
        { PERIPH_ID_DVC_I2C, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
        { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },

diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c
index 36c35c608b29dcbdad233ef22cca5195e29ed939..95fc26458b89d4f6e5619465de1bd2699aa5fa16 100644 (file)
--- a/drivers/pwm/tegra_pwm.c
+++ b/drivers/pwm/tegra_pwm.c
@@ -20,19 +20,21 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel,
 {
        struct tegra_pwm_priv *priv = dev_get_priv(dev);
        struct pwm_ctlr *regs = priv->regs;
+       const u32 pwm_max_freq = dev_get_driver_data(dev);
        uint pulse_width;
        u32 reg;
 
        if (channel >= 4)
                return -EINVAL;
        debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
-       /* We ignore the period here and just use 32KHz */
-       clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
+
+       clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq);
 
        pulse_width = duty_ns * 255 / period_ns;
 
        reg = pulse_width << PWM_WIDTH_SHIFT;
        reg |= 1 << PWM_DIVIDER_SHIFT;
+       reg |= PWM_ENABLE_MASK;
        writel(reg, &regs[channel].control);
        debug("%s: pulse_width=%u\n", __func__, pulse_width);
 
@@ -68,8 +70,8 @@ static const struct pwm_ops tegra_pwm_ops = {
 };
 
 static const struct udevice_id tegra_pwm_ids[] = {
-       { .compatible = "nvidia,tegra124-pwm" },
-       { .compatible = "nvidia,tegra20-pwm" },
+       { .compatible = "nvidia,tegra20-pwm", .data = 48 * 1000000 },
+       { .compatible = "nvidia,tegra114-pwm", .data = 408 * 1000000 },
        { }
 };