mpc85xx/t104xrdb : remove raw timing parameter

This board uses DDR DIMM. Reading SPD provides more flexibility.
Raw timing parameter code should be removed after debugging.

Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index 5aa11b12a46ec44619b6a0598a6929b9e6b9b29a..e1148e568e8ee66a9ae36adf0764083a81621a84 100644 (file)
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -16,21 +16,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-               unsigned int controller_number,
-               unsigned int dimm_number)
-{
-       const char dimm_model[] = "RAW timing DDR";
-
-       if ((controller_number == 0) && (dimm_number == 0)) {
-               memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-               memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-               memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-       }
-
-       return 0;
-}
-
 void fsl_ddr_board_options(memctl_options_t *popts,
                                dimm_params_t *pdimm,
                                unsigned int ctrl_num)

diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index 09b30b9aac7f041a620dd67f1478122e55f302ef..ab1c32d10e791ab0a8f4d56f927b73d6215d8ed8 100644 (file)
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -6,35 +6,6 @@
 
 #ifndef __DDR_H__
 #define __DDR_H__
-dimm_params_t ddr_raw_timing = {
-       .n_ranks = 2,
-       .rank_density = 2147483648u,
-       .capacity = 4294967296u,
-       .primary_sdram_width = 64,
-       .ec_sdram_width = 8,
-       .registered_dimm = 0,
-       .mirrored_dimm = 0,
-       .n_row_addr = 15,
-       .n_col_addr = 10,
-       .n_banks_per_sdram_device = 8,
-       .edc_config = 2,        /* ECC */
-       .burst_lengths_bitmask = 0x0c,
-       .tckmin_x_ps = 1071,
-       .caslat_x = 0xfe << 4,  /* 5,6,7,8,9,10,11 */
-       .taa_ps = 13125,
-       .twr_ps = 15000,
-       .trcd_ps = 13125,
-       .trrd_ps = 6000,
-       .trp_ps = 13125,
-       .tras_ps = 34000,
-       .trc_ps = 48125,
-       .trfc_ps = 260000,
-       .twtr_ps = 7500,
-       .trtp_ps = 7500,
-       .refresh_rate_ps = 7800000,
-       .tfaw_ps = 35000,
-};
-
 struct board_specific_parameters {
        u32 n_ranks;
        u32 datarate_mhz_high;

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index d47f1be6851188650e1d315e586905ed1fcdf5f3..52633181ad4e990ba91eff154c338e8f4312126b 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -220,7 +220,6 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 
 #define CONFIG_DDR_SPD
-#define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_SYS_FSL_DDR3
 
 #define CONFIG_SYS_SPD_BUS_NUM 0