imx: Add auto generation of asm-offsets.h for imx25

Offsets to registers may be needed in asm code. This patch adds automated
generation of these offsets form C structures.

Signed-off-by: Matthias Weisser <weisserm@arcor.de>

diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile
index 3c2a65ed79e9949c7f6d0bc586222288b0929324..9219c062b01f285aa798149aec8f047f04245236 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mx25/Makefile
+++ b/arch/arm/cpu/arm926ejs/mx25/Makefile
@@ -34,6 +34,8 @@ all:  $(obj).depend $(LIB)
 $(LIB):        $(OBJS)
        $(call cmd_link_o_target, $(OBJS))
 
+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h
+
 #########################################################################
 
 # defines $(obj).depend target

diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
new file mode 100644 (file)
index 0000000..ba8dfd4
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c
@@ -0,0 +1,60 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/arch/imx-regs.h>
+
+#include <linux/kbuild.h>
+
+int main(void)
+{
+       /* Clock Control Module */
+       DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
+       DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
+       DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
+       DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
+       DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
+       DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
+
+       /* Enhanced SDRAM Controller */
+       DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
+       DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
+       DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
+
+       /* Multi-Layer AHB Crossbar Switch */
+       DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+       DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+       DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+       DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+       DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+       DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+       DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+       DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+       DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+       DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+       DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+       DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+       DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+       DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+       DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+
+       /* AHB <-> IP-Bus Interface */
+       DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+       DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+
+       return 0;
+}

diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 55ad115a76fb43ae5ba186dff5f608cd6517988c..62ee4d537b76ebf0a8beda12e380abc7bb851885 100644 (file)
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -141,6 +141,45 @@ struct fuse_bank0_regs {
        u32 mac_addr[6];
 };
 
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+       u32 mpr0;
+       u32 pad00[3];
+       u32 sgpcr0;
+       u32 pad01[59];
+       u32 mpr1;
+       u32 pad02[3];
+       u32 sgpcr1;
+       u32 pad03[59];
+       u32 mpr2;
+       u32 pad04[3];
+       u32 sgpcr2;
+       u32 pad05[59];
+       u32 mpr3;
+       u32 pad06[3];
+       u32 sgpcr3;
+       u32 pad07[59];
+       u32 mpr4;
+       u32 pad08[3];
+       u32 sgpcr4;
+       u32 pad09[251];
+       u32 mgpcr0;
+       u32 pad10[63];
+       u32 mgpcr1;
+       u32 pad11[63];
+       u32 mgpcr2;
+       u32 pad12[63];
+       u32 mgpcr3;
+       u32 pad13[63];
+       u32 mgpcr4;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+       u32 mpr_0_7;
+       u32 mpr_8_15;
+};
+
 #endif
 
 /* AIPS 1 */