Merge tag 'v2021.04-rc4' into next

Prepare v2021.04-rc4

diff --cc Makefile
Simple merge

diff --cc arch/arm/mach-imx/imx8m/soc.c
Simple merge

diff --cc arch/arm/mach-socfpga/include/mach/reset_manager.h
Simple merge

diff --cc arch/arm/mach-stm32mp/cpu.c
index d332f5aecd00920ac400a4d2ec1137d604e25f2f,bc2db535beb09b073433c61ae215193c4efc073f..897ec13ad819c1f6e305016caeb17d121d684e32
--- 1/arch/arm/mach-stm32mp/cpu.c
--- 2/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@@ -252,11 -223,22 +252,13 @@@ static void early_enable_caches(void
        if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
                return;
  
-       gd->arch.tlb_size = PGTABLE_SIZE;
-       gd->arch.tlb_addr = (unsigned long)&early_tlb;
+       if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) {
+               gd->arch.tlb_size = PGTABLE_SIZE;
+               gd->arch.tlb_addr = (unsigned long)&early_tlb;
+       }
  
 +      /* enable MMU (default configuration) */
        dcache_enable();
 -
 -      if (IS_ENABLED(CONFIG_SPL_BUILD))
 -              mmu_set_region_dcache_behaviour(
 -                      ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE),
 -                      ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE),
 -                      DCACHE_DEFAULT_OPTION);
 -      else
 -              mmu_set_region_dcache_behaviour(STM32_DDR_BASE,
 -                                              CONFIG_DDR_CACHEABLE_SIZE,
 -                                              DCACHE_DEFAULT_OPTION);
  }
  
  /*

diff --cc cmd/Kconfig
Simple merge

diff --cc cmd/Makefile
Simple merge

diff --cc doc/usage/index.rst
Simple merge

diff --cc drivers/sysreset/sysreset-uclass.c
Simple merge

diff --cc scripts/config_whitelist.txt
Simple merge

diff --cc test/cmd_ut.c
Simple merge

diff --cc test/unicode_ut.c
Simple merge