fsl-ddr: make the self refresh idle threshold configurable

Some 85xx processors have the advanced power management feature,
such as wake up ARP, that needs enable the automatic self refresh.

If the DDR controller pass the SR_IT (self refresh idle threshold)
idle cycles, it will automatically enter self refresh. However,
anytime one transaction is issued to the DDR controller, it will
reset the counter and exit self refresh state.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index eae794c76f44f177880ae2f7c7fac78658d09b59..292980d0b073a885a440fd683a61161d0017f7e2 100644 (file)
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -755,10 +755,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr)
 }
 
 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
-static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr)
+static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
 {
-       unsigned int sr_it = 0; /* Self Refresh Idle Threshold */
-
+       /* Self Refresh Idle Threshold */
        ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
 }
 
@@ -861,6 +860,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        unsigned int i;
        unsigned int cas_latency;
        unsigned int additive_latency;
+       unsigned int sr_it;
 
        memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
 
@@ -882,6 +882,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
                ? popts->additive_latency_override_value
                : common_dimm->additive_latency;
 
+       sr_it = (popts->auto_self_refresh_en)
+               ? popts->sr_it
+               : 0;
+
        /* Chip Select Memory Bounds (CSn_BNDS) */
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
                phys_size_t sa = 0;
@@ -1042,7 +1046,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
        set_ddr_wrlvl_cntl(ddr);
 
        set_ddr_pd_cntl(ddr);
-       set_ddr_sr_cntr(ddr);
+       set_ddr_sr_cntr(ddr, sr_it);
 
        set_ddr_sdram_rcw_1(ddr);
        set_ddr_sdram_rcw_2(ddr);

diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 0006c21a0236be5ff600f7a7ef3caad19df76a3e..b213af35ef362f5dc894ea4ef46bb84e4dda6ea4 100644 (file)
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -146,6 +146,10 @@ typedef struct memctl_options_s {
        unsigned int bstopre;
        unsigned int tCKE_clock_pulse_width_ps; /* tCKE */
        unsigned int tFAW_window_four_activates_ps;     /* tFAW --  FOUR_ACT */
+
+       /* Automatic self refresh */
+       unsigned int auto_self_refresh_en;
+       unsigned int sr_it;
 } memctl_options_t;
 
 extern phys_size_t fsl_ddr_sdram(void);