mxs: Fix VDDx brownout interrupt disable/enable

Incorrect registers HW_POWER_VDDIOCTRL, HW_POWER_VDDACTRL
and HW_POWER_VDDDCTRL are used in the current code to disable/enable
brownout interrupts in 'mxs_power_set_vddx()'.
Change register to HW_POWER_CTRL which contains brownout interrupt
enable bits ENIRQ_VDDIO_BO, ENIRQ_VDDA_BO and ENIRQ_VDDD_BO.

Signed-off-by: Cody Green <cody@londelec.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 7ea029e37120719ffc17f532b7e59f8765542c30..77bca7e331a07166132f83b7a432936cd5d82aa7 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -1177,8 +1177,9 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
 
        if (adjust_up && cfg->bo_irq) {
                if (powered_by_linreg) {
-                       bo_int = readl(cfg->reg);
-                       clrbits_le32(cfg->reg, cfg->bo_enirq);
+                       bo_int = readl(&power_regs->hw_power_ctrl);
+                       clrbits_le32(&power_regs->hw_power_ctrl,
+                               cfg->bo_enirq);
                }
                setbits_le32(cfg->reg, cfg->bo_offset_mask);
        }
@@ -1220,7 +1221,8 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
                if (adjust_up && powered_by_linreg) {
                        writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
                        if (bo_int & cfg->bo_enirq)
-                               setbits_le32(cfg->reg, cfg->bo_enirq);
+                               setbits_le32(&power_regs->hw_power_ctrl,
+                                       cfg->bo_enirq);
                }
 
                clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,