riscv: lib: implement enable_caches for sifive cache

The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4b0c3dffa6b1e3a8a57304069e6d1dcfb564c58f..ec651fe0a41d1d56bdeb3bc1416f8b5c479b10d0 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
          The SiFive CLINT block holds memory-mapped control and status registers
          associated with software and timer interrupts.
 
+config SIFIVE_CACHE
+       bool
+       help
+         This enables the operations to configure SiFive cache
+
 config ANDES_PLIC
        bool
        depends on RISCV_MMODE || SPL_RISCV_MMODE

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index c4cc41434b0b4ca5b4f924b5e26c81930c9c626a..06020fcc2ad400a10947ac24319f6728cdbc43d4 100644 (file)
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
+obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
 ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o

diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
new file mode 100644 (file)
index 0000000..2815487
--- /dev/null
+++ b/arch/riscv/lib/sifive_cache.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 SiFive, Inc
+ */
+
+#include <common.h>
+#include <cache.h>
+#include <cpu_func.h>
+#include <dm.h>
+
+void enable_caches(void)
+{
+       struct udevice *dev;
+       int ret;
+
+       /* Enable ways of ccache */
+       ret = uclass_get_device_by_driver(UCLASS_CACHE,
+                                         DM_DRIVER_GET(sifive_ccache),
+                                         &dev);
+       if (ret) {
+               log_debug("Cannot enable cache ways");
+       } else {
+               ret = cache_enable(dev);
+               if (ret)
+                       log_debug("ccache enable failed");
+       }
+}