board/BuR: fix pinmux for MII Ethernet Interface

The lines COL (collision detect) and CRS (carrier sense) needs to be connected
and muxed to the CPSW MAC for a proper function in half-duplex Mode of the
interface.

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Tom Rini <trini@ti.com>

diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
index 1a5ffd57099f214e24d619ebaec66a7a89849428..ecb2e7a4275e9f229b4ee2c2b7e42c40b8cecd0e 100644 (file)
--- a/board/BuR/kwb/mux.c
+++ b/board/BuR/kwb/mux.c
@@ -105,6 +105,8 @@ static struct module_pin_mux i2c0_pin_mux[] = {
 };
 
 static struct module_pin_mux mii1_pin_mux[] = {
+       {OFFSET(mii1_crs), MODE(0) | RXACTIVE},         /* MII1_CRS */
+       {OFFSET(mii1_col), MODE(0) | RXACTIVE},         /* MII1_COL */
        {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},       /* MII1_RXERR */
        {OFFSET(mii1_txen), MODE(0)},                   /* MII1_TXEN */
        {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},        /* MII1_RXDV */

diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
index 210ac71738818794a994d30a0d34ea4d36c2c1cb..0ba25ee31863161da410d449504e81d1c6bb057b 100644 (file)
--- a/board/BuR/tseries/mux.c
+++ b/board/BuR/tseries/mux.c
@@ -64,6 +64,8 @@ static struct module_pin_mux spi0_pin_mux[] = {
 };
 
 static struct module_pin_mux mii1_pin_mux[] = {
+       {OFFSET(mii1_crs), MODE(0) | RXACTIVE},         /* MII1_CRS */
+       {OFFSET(mii1_col), MODE(0) | RXACTIVE},         /* MII1_COL */
        {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},       /* MII1_RXERR */
        {OFFSET(mii1_txen), MODE(0)},                   /* MII1_TXEN */
        {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},        /* MII1_RXDV */
@@ -96,6 +98,7 @@ static struct module_pin_mux mii2_pin_mux[] = {
        {OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
        {OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
        {OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+       {OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
                                                /*
                                                 * MII2_CRS is shared with
                                                 * NAND_WAIT0