};
clocks {
- u-boot,dm-spl;
-
osc: osc {
- u-boot,dm-spl;
compatible = "fsl,imx-osc", "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
soc {
- u-boot,dm-spl;
-
semc: semc@402f0000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-semc";
reg = <0x402f0000 0x4000>;
clocks = <&clks IMXRT1050_CLK_SEMC>;
};
clks: ccm@400fc000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
};
usdhc1: usdhc@402c0000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-usdhc";
reg = <0x402c0000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
};
gpio1: gpio@401b8000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
};
gpio2: gpio@401bc000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
};
gpio3: gpio@401c0000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
};
gpio4: gpio@401c4000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x401c4000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
};
gpio5: gpio@400c0000 {
- u-boot,dm-spl;
compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,