powerpc/P4080: Check SVR for CPU22 workaround

Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 2ed5a98424f1a92745db5a8d76d1c21f404ace83..d7a62e9c76333c4da3444134efa6e04326122523 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -51,7 +51,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
        puts("Work-around for Erratum SERDES-A005 enabled\n");
 #endif
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-       puts("Work-around for Erratum CPU22 enabled\n");
+       if (SVR_MAJ(svr) < 3)
+               puts("Work-around for Erratum CPU22 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
        puts("Work-around for Erratum CPU-A003999 enabled\n");

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e7b2d377938debebc9fa6a27196e8dc81eaa5a1e..b64eda3eb63b6c9fd8f2a998e527e1fdbf17606c 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -309,9 +309,11 @@ int cpu_init_r(void)
 #endif
 
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-       flush_dcache();
-       mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
-       sync();
+       if (SVR_MAJ(svr) < 3) {
+               flush_dcache();
+               mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
+               sync();
+       }
 #endif
 
        puts ("L2:    ");

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index c81e19c0e99bc5231d8a3c32b166d47373a2b84f..fe3b6d6cbcd411586af72496bd87e40cc57b41d8 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -144,9 +144,17 @@ __secondary_start_page:
 #endif
 
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
+       /* apply to P4080 rev 1 and rev 2 */
+       mfspr   r3,SPRN_SVR
+       rlwinm  r3,r3,0,0xf0
+       li      r4,0x30
+       cmpw    r3,r4
+       bge     2f
+
        mfspr   r8,L1CSR2
        oris    r8,r8,(L1CSR2_DCWS)@h
        mtspr   L1CSR2,r8
+2:
 #endif
 
 #ifdef CONFIG_BACKSIDE_L2_CACHE