nand_spl: Fix cmd_ctrl usage in nand_boot.c.

When adding large page NAND support to this file, I had a misunderstanding
about the exact semantics of NAND_CTRL_CHANGE (which isn't documented
anywhere I can find) -- it is apparently just a hint to drivers,
which aren't required to preserve the old value for subsequent
non-"change" invocations.

This change makes nand_boot.c no longer assume this.  Note that this
happened to work by chance with some NAND drivers, which don't preserve
the value, but treat 0 equivalently to NAND_CTRL_ALE.

I don't have hardware to test this, so any testing is appreciated.

Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c
index be2e69c287c741b5efa570e84565a37c0c717808..b9fd6f544c94beac65f6feb0a3f473b383df43a7 100644 (file)
--- a/nand_spl/nand_boot.c
+++ b/nand_spl/nand_boot.c
@@ -47,11 +47,13 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
        /* Set ALE and clear CLE to start address cycle */
        /* Column address */
        this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
-       this->cmd_ctrl(mtd, page_addr & 0xff, 0); /* A[16:9] */
-       this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff, 0); /* A[24:17] */
+       this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
+       this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
+                      NAND_CTRL_ALE); /* A[24:17] */
 #ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
        /* One more address cycle for devices > 32MiB */
-       this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[28:25] */
+       this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
+                      NAND_CTRL_ALE); /* A[28:25] */
 #endif
        /* Latch in address */
        this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
@@ -94,13 +96,15 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8
        /* Column address */
        this->cmd_ctrl(mtd, offs & 0xff,
                       NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
-       this->cmd_ctrl(mtd, (offs >> 8) & 0xff, 0); /* A[11:9] */
+       this->cmd_ctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
        /* Row address */
-       this->cmd_ctrl(mtd, (page_addr & 0xff), 0); /* A[19:12] */
-       this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff), 0); /* A[27:20] */
+       this->cmd_ctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
+       this->cmd_ctrl(mtd, ((page_addr >> 8) & 0xff),
+                      NAND_CTRL_ALE); /* A[27:20] */
 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
        /* One more address cycle for devices > 128MiB */
-       this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f, 0); /* A[31:28] */
+       this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
+                      NAND_CTRL_ALE); /* A[31:28] */
 #endif
        /* Latch in address */
        this->cmd_ctrl(mtd, NAND_CMD_READSTART,