arch: powerpc: update the IFC IP input clock

IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.

Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/README b/README
index a95348a876b4a53609ca5e384df5cc49abc61ac2..9fda38109de737c51b25cbefca338bda8a7a6604 100644 (file)
--- a/README
+++ b/README
@@ -504,6 +504,9 @@ The following options need to be configured:
                CONFIG_SYS_FSL_IFC_LE
                Defines the IFC controller register space as Little Endian
 
+               CONFIG_SYS_FSL_IFC_CLK_DIV
+               Defines divider of platform clock(clock input to IFC controller).
+
                CONFIG_SYS_FSL_PBL_PBI
                It enables addition of RCW (Power on reset configuration) in built image.
                Please refer doc/README.pblimage for more details

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index a3db01407ce7f3fd9813baed7ec62ba755bef402..83df73369805aa259ab25b9fa171e3eb0b164917 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1301,6 +1301,22 @@ config SYS_PPC_E500_DEBUG_TLB
                 symbol should be set to the TLB1 entry to be used for this
                 purpose. If unsure, do not change.
 
+config SYS_FSL_IFC_CLK_DIV
+       int "Divider of platform clock"
+       depends on FSL_IFC
+       default 2 if    ARCH_B4420      || \
+                       ARCH_B4860      || \
+                       ARCH_T1024      || \
+                       ARCH_T1023      || \
+                       ARCH_T1040      || \
+                       ARCH_T1042      || \
+                       ARCH_T4160      || \
+                       ARCH_T4240
+       default 1
+       help
+               Defines divider of platform clock(clock input to
+               IFC controller).
+
 source "board/freescale/b4860qds/Kconfig"
 source "board/freescale/bsc9131rdb/Kconfig"
 source "board/freescale/bsc9132qds/Kconfig"

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index fcf5d92af518dfcf6770939adc8b16e9c28cd4dc..adba0925b7f6d02537abd90984e031a87052230d 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info(sys_info_t *sys_info)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#ifdef CONFIG_FSL_IFC
-       struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
-       u32 ccr;
-#endif
 #ifdef CONFIG_FSL_CORENET
        volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
        unsigned int cpu;
@@ -640,10 +636,8 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-       ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
-       ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
-
-       sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+       sys_info->freq_localbus = sys_info->freq_systembus /
+                                               CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
 }