powerpc/t4rdb: Fix CPLD timing

This fixes CPLD timing from previous commit
ab06b236f76cfa42f264ee161be190b3e479298f.

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: This is the difference between v2 and v1 patch]
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index e639e1d57af0f5c88e15b948785593ecb33f1747..48b8dc7fd71f1362dbf1fe19e094d730323ece3c 100644 (file)
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -533,7 +533,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS3_FTIM1           (FTIM1_GPCM_TACO(0x0e) | \
                                        FTIM1_GPCM_TRAD(0x1f))
 #define CONFIG_SYS_CS3_FTIM2           (FTIM2_GPCM_TCS(0x0e) | \
-                                       FTIM2_GPCM_TCH(0x0) | \
+                                       FTIM2_GPCM_TCH(0x8) | \
                                        FTIM2_GPCM_TWP(0x1f))
 #define CONFIG_SYS_CS3_FTIM3           0x0