arm: dts: Introduce base AM62 SoC dtsi files

Introduce the basic AM62 SoC description dtsi files describing most
peripherals as per kernel dts.

Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm/dts/k3-am62-ddr.dtsi b/arch/arm/dts/k3-am62-ddr.dtsi
new file mode 100644 (file)
index 0000000..0a8ced8
--- /dev/null
+++ b/arch/arm/dts/k3-am62-ddr.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "k3-am64-ddr.dtsi"
+&memorycontroller {
+       power-domains = <&k3_pds 170 TI_SCI_PD_SHARED>,
+                       <&k3_pds 55 TI_SCI_PD_SHARED>;
+       clocks = <&k3_clks 170 0>, <&k3_clks 16 4>;
+};

diff --git a/arch/arm/dts/k3-am62-main.dtsi b/arch/arm/dts/k3-am62-main.dtsi
new file mode 100644 (file)
index 0000000..4b6ba98
--- /dev/null
+++ b/arch/arm/dts/k3-am62-main.dtsi
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+       oc_sram: sram@70000000 {
+               compatible = "mmio-sram";
+               reg = <0x00 0x70000000 0x00 0x10000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x00 0x70000000 0x10000>;
+       };
+
+       gic500: interrupt-controller@1800000 {
+               compatible = "arm,gic-v3";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
+                     <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
+                     <0x00 0x01880000 0x00 0xc0000>,   /* GICR */
+                     <0x01 0x00000000 0x00 0x2000>,    /* GICC */
+                     <0x01 0x00010000 0x00 0x1000>,    /* GICH */
+                     <0x01 0x00020000 0x00 0x2000>;    /* GICV */
+               /*
+                * vcpumntirq:
+                * virtual CPU interface maintenance interrupt
+                */
+               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+               gic_its: msi-controller@1820000 {
+                       compatible = "arm,gic-v3-its";
+                       reg = <0x00 0x01820000 0x00 0x10000>;
+                       socionext,synquacer-pre-its = <0x1000000 0x400000>;
+                       msi-controller;
+                       #msi-cells = <1>;
+               };
+       };
+
+       main_conf: syscon@100000 {
+               compatible = "syscon", "simple-mfd";
+               reg = <0x00 0x00100000 0x00 0x20000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x00 0x00100000 0x20000>;
+
+               phy_gmii_sel: phy@4044 {
+                       compatible = "ti,am654-phy-gmii-sel";
+                       reg = <0x4044 0x8>;
+                       #phy-cells = <1>;
+               };
+       };
+
+       dmss: bus@48000000 {
+               compatible = "simple-mfd";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               dma-ranges;
+               ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
+
+               ti,sci-dev-id = <25>;
+
+               secure_proxy_main: mailbox@4d000000 {
+                       compatible = "ti,am654-secure-proxy";
+                       #mbox-cells = <1>;
+                       reg-names = "target_data", "rt", "scfg";
+                       reg = <0x00 0x4d000000 0x00 0x80000>,
+                             <0x00 0x4a600000 0x00 0x80000>,
+                             <0x00 0x4a400000 0x00 0x80000>;
+                       interrupt-names = "rx_012";
+                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               inta_main_dmss: interrupt-controller@48000000 {
+                       compatible = "ti,sci-inta";
+                       reg = <0x00 0x48000000 0x00 0x100000>;
+                       #interrupt-cells = <0>;
+                       interrupt-controller;
+                       interrupt-parent = <&gic500>;
+                       msi-controller;
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <28>;
+                       ti,interrupt-ranges = <4 68 36>;
+                       ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+               };
+
+               main_bcdma: dma-controller@485c0100 {
+                       compatible = "ti,am64-dmss-bcdma";
+                       reg = <0x00 0x485c0100 0x00 0x100>,
+                             <0x00 0x4c000000 0x00 0x20000>,
+                             <0x00 0x4a820000 0x00 0x20000>,
+                             <0x00 0x4aa40000 0x00 0x20000>,
+                             <0x00 0x4bc00000 0x00 0x100000>;
+                       reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+                       msi-parent = <&inta_main_dmss>;
+                       #dma-cells = <3>;
+
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <26>;
+                       ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+                       ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+                       ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+               };
+
+               main_pktdma: dma-controller@485c0000 {
+                       compatible = "ti,am64-dmss-pktdma";
+                       reg = <0x00 0x485c0000 0x00 0x100>,
+                             <0x00 0x4a800000 0x00 0x20000>,
+                             <0x00 0x4aa00000 0x00 0x40000>,
+                             <0x00 0x4b800000 0x00 0x400000>;
+                       reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+                       msi-parent = <&inta_main_dmss>;
+                       #dma-cells = <2>;
+
+                       ti,sci = <&dmsc>;
+                       ti,sci-dev-id = <30>;
+                       ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+                                               <0x24>, /* CPSW_TX_CHAN */
+                                               <0x25>, /* SAUL_TX_0_CHAN */
+                                               <0x26>; /* SAUL_TX_1_CHAN */
+                       ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+                                               <0x11>, /* RING_CPSW_TX_CHAN */
+                                               <0x12>, /* RING_SAUL_TX_0_CHAN */
+                                               <0x13>; /* RING_SAUL_TX_1_CHAN */
+                       ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+                                               <0x2b>, /* CPSW_RX_CHAN */
+                                               <0x2d>, /* SAUL_RX_0_CHAN */
+                                               <0x2f>, /* SAUL_RX_1_CHAN */
+                                               <0x31>, /* SAUL_RX_2_CHAN */
+                                               <0x33>; /* SAUL_RX_3_CHAN */
+                       ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+                                               <0x2c>, /* FLOW_CPSW_RX_CHAN */
+                                               <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+                                               <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */
+               };
+       };
+
+       dmsc: system-controller@44043000 {
+               compatible = "ti,k2g-sci";
+               ti,host-id = <12>;
+               mbox-names = "rx", "tx";
+               mboxes= <&secure_proxy_main 12>,
+                       <&secure_proxy_main 13>;
+               reg-names = "debug_messages";
+               reg = <0x00 0x44043000 0x00 0xfe0>;
+
+               k3_pds: power-controller {
+                       compatible = "ti,sci-pm-domain";
+                       #power-domain-cells = <2>;
+               };
+
+               k3_clks: clock-controller {
+                       compatible = "ti,k2g-sci-clk";
+                       #clock-cells = <2>;
+               };
+
+               k3_reset: reset-controller {
+                       compatible = "ti,sci-reset";
+                       #reset-cells = <2>;
+               };
+       };
+
+       main_pmx0: pinctrl@f4000 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0xf4000 0x00 0x2ac>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0xffffffff>;
+       };
+
+       main_uart0: serial@2800000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x02800000 0x00 0x100>;
+               interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 146 0>;
+               clock-names = "fclk";
+       };
+
+       main_uart1: serial@2810000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x02810000 0x00 0x100>;
+               interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 152 0>;
+               clock-names = "fclk";
+       };
+
+       main_uart2: serial@2820000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x02820000 0x00 0x100>;
+               interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 153 0>;
+               clock-names = "fclk";
+       };
+
+       main_uart3: serial@2830000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x02830000 0x00 0x100>;
+               interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 154 0>;
+               clock-names = "fclk";
+       };
+
+       main_uart4: serial@2840000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x02840000 0x00 0x100>;
+               interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 155 0>;
+               clock-names = "fclk";
+       };
+
+       main_uart5: serial@2850000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x02850000 0x00 0x100>;
+               interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 156 0>;
+               clock-names = "fclk";
+       };
+
+       main_uart6: serial@2860000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x02860000 0x00 0x100>;
+               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 158 0>;
+               clock-names = "fclk";
+       };
+
+       main_i2c0: i2c@20000000 {
+               compatible = "ti,am64-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x20000000 0x00 0x100>;
+               interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 102 2>;
+               clock-names = "fck";
+       };
+
+       main_i2c1: i2c@20010000 {
+               compatible = "ti,am64-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x20010000 0x00 0x100>;
+               interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 103 2>;
+               clock-names = "fck";
+       };
+
+       main_i2c2: i2c@20020000 {
+               compatible = "ti,am64-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x20020000 0x00 0x100>;
+               interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 104 2>;
+               clock-names = "fck";
+       };
+
+       main_i2c3: i2c@20030000 {
+               compatible = "ti,am64-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x20030000 0x00 0x100>;
+               interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 105 2>;
+               clock-names = "fck";
+       };
+
+       main_spi0: spi@20100000 {
+               compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+               reg = <0x00 0x20100000 0x00 0x400>;
+               interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 172 0>;
+       };
+
+       main_spi1: spi@20110000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x20110000 0x00 0x400>;
+               interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 173 0>;
+       };
+
+       main_spi2: spi@20120000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x20120000 0x00 0x400>;
+               interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 174 0>;
+       };
+
+       main_gpio_intr: interrupt-controller@a00000 {
+               compatible = "ti,sci-intr";
+               reg = <0x00 0x00a00000 0x00 0x800>;
+               ti,intr-trigger-type = <1>;
+               interrupt-controller;
+               interrupt-parent = <&gic500>;
+               #interrupt-cells = <1>;
+               ti,sci = <&dmsc>;
+               ti,sci-dev-id = <3>;
+               ti,interrupt-ranges = <0 32 16>;
+       };
+
+       main_gpio0: gpio@600000 {
+               compatible = "ti,am64-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00600000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <190>, <191>, <192>,
+                            <193>, <194>, <195>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <87>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 77 0>;
+               clock-names = "gpio";
+       };
+
+       main_gpio1: gpio@601000 {
+               compatible = "ti,am64-gpio", "ti,keystone-gpio";
+               reg = <0x0 0x00601000 0x0 0x100>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-parent = <&main_gpio_intr>;
+               interrupts = <180>, <181>, <182>,
+                            <183>, <184>, <185>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+               ti,ngpio = <88>;
+               ti,davinci-gpio-unbanked = <0>;
+               power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 78 0>;
+               clock-names = "gpio";
+       };
+
+       sdhci0: mmc@fa10000 {
+               compatible = "ti,am62-sdhci";
+               reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
+               interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
+               clock-names = "clk_ahb", "clk_xin";
+               assigned-clocks = <&k3_clks 57 6>;
+               assigned-clock-parents = <&k3_clks 57 8>;
+               mmc-ddr-1_8v;
+               mmc-hs200-1_8v;
+               ti,trm-icp = <0x2>;
+               bus-width = <8>;
+               ti,clkbuf-sel = <0x7>;
+               ti,otap-del-sel-legacy = <0x0>;
+               ti,otap-del-sel-mmc-hs = <0x0>;
+               ti,otap-del-sel-ddr52 = <0x9>;
+               ti,otap-del-sel-hs200 = <0x6>;
+       };
+
+       sdhci1: mmc@fa00000 {
+               compatible = "ti,am62-sdhci";
+               reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>;
+               interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 58 5>, <&k3_clks 58 6>;
+               clock-names = "clk_ahb", "clk_xin";
+               ti,trm-icp = <0x2>;
+               ti,otap-del-sel-legacy = <0x0>;
+               ti,otap-del-sel-sd-hs = <0x0>;
+               ti,otap-del-sel-sdr12 = <0xf>;
+               ti,otap-del-sel-sdr25 = <0xf>;
+               ti,otap-del-sel-sdr50 = <0xc>;
+               ti,otap-del-sel-sdr104 = <0x6>;
+               ti,otap-del-sel-ddr50 = <0x9>;
+               ti,itap-del-sel-legacy = <0x0>;
+               ti,itap-del-sel-sd-hs = <0x0>;
+               ti,itap-del-sel-sdr12 = <0x0>;
+               ti,itap-del-sel-sdr25 = <0x0>;
+               ti,clkbuf-sel = <0x7>;
+               bus-width = <4>;
+       };
+
+       sdhci2: mmc@fa20000 {
+               compatible = "ti,am62-sdhci";
+               reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>;
+               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 184 5>, <&k3_clks 184 6>;
+               clock-names = "clk_ahb", "clk_xin";
+               ti,trm-icp = <0x2>;
+               ti,otap-del-sel-legacy = <0x0>;
+               ti,otap-del-sel-sd-hs = <0x0>;
+               ti,otap-del-sel-sdr12 = <0xf>;
+               ti,otap-del-sel-sdr25 = <0xf>;
+               ti,otap-del-sel-sdr50 = <0xc>;
+               ti,otap-del-sel-sdr104 = <0x6>;
+               ti,otap-del-sel-ddr50 = <0x9>;
+               ti,itap-del-sel-legacy = <0x0>;
+               ti,itap-del-sel-sd-hs = <0x0>;
+               ti,itap-del-sel-sdr12 = <0x0>;
+               ti,itap-del-sel-sdr25 = <0x0>;
+               ti,clkbuf-sel = <0x7>;
+       };
+
+       fss: bus@fc00000 {
+               compatible = "simple-bus";
+               reg = <0x00 0x0fc00000 0x00 0x70000>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               ospi0: spi@fc40000 {
+                       compatible = "ti,am654-ospi", "cdns,qspi-nor";
+                       reg = <0x00 0x0fc40000 0x00 0x100>,
+                             <0x05 0x00000000 0x01 0x00000000>;
+                       interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       cdns,trigger-address = <0x0>;
+                       clocks = <&k3_clks 75 7>;
+                       assigned-clocks = <&k3_clks 75 7>;
+                       assigned-clock-parents = <&k3_clks 75 8>;
+                       assigned-clock-rates = <166666666>;
+                       power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+
+       cpsw3g: ethernet@8000000 {
+               compatible = "ti,am642-cpsw-nuss";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               reg = <0x00 0x08000000 0x00 0x200000>;
+               reg-names = "cpsw_nuss";
+               ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>;
+               clocks = <&k3_clks 13 0>;
+               assigned-clocks = <&k3_clks 13 3>;
+               assigned-clock-parents = <&k3_clks 13 11>;
+               clock-names = "fck";
+               power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+
+               dmas = <&main_pktdma 0xc600 15>,
+                      <&main_pktdma 0xc601 15>,
+                      <&main_pktdma 0xc602 15>,
+                      <&main_pktdma 0xc603 15>,
+                      <&main_pktdma 0xc604 15>,
+                      <&main_pktdma 0xc605 15>,
+                      <&main_pktdma 0xc606 15>,
+                      <&main_pktdma 0xc607 15>,
+                      <&main_pktdma 0x4600 15>;
+               dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+                           "tx7", "rx";
+
+               ethernet-ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       cpsw_port1: port@1 {
+                               reg = <1>;
+                               ti,mac-only;
+                               label = "port1";
+                               phys = <&phy_gmii_sel 1>;
+                               mac-address = [00 00 00 00 00 00];
+                               ti,syscon-efuse = <&wkup_conf 0x200>;
+                       };
+
+                       cpsw_port2: port@2 {
+                               reg = <2>;
+                               ti,mac-only;
+                               label = "port2";
+                               phys = <&phy_gmii_sel 2>;
+                               mac-address = [00 00 00 00 00 00];
+                       };
+               };
+
+               cpsw3g_mdio: mdio@f00 {
+                       compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+                       reg = <0x00 0xf00 0x00 0x100>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&k3_clks 13 0>;
+                       clock-names = "fck";
+                       bus_freq = <1000000>;
+               };
+
+               cpts@3d000 {
+                       compatible = "ti,j721e-cpts";
+                       reg = <0x00 0x3d000 0x00 0x400>;
+                       clocks = <&k3_clks 13 1>;
+                       clock-names = "cpts";
+                       interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "cpts";
+                       ti,cpts-ext-ts-inputs = <4>;
+                       ti,cpts-periodic-outputs = <2>;
+               };
+       };
+
+       hwspinlock: spinlock@2a000000 {
+               compatible = "ti,am64-hwspinlock";
+               reg = <0x00 0x2a000000 0x00 0x1000>;
+               #hwlock-cells = <1>;
+       };
+
+       mailbox0_cluster0: mailbox@29000000 {
+               compatible = "ti,am64-mailbox";
+               reg = <0x00 0x29000000 0x00 0x200>;
+               interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+               #mbox-cells = <1>;
+               ti,mbox-num-users = <4>;
+               ti,mbox-num-fifos = <16>;
+       };
+};

diff --git a/arch/arm/dts/k3-am62-mcu.dtsi b/arch/arm/dts/k3-am62-mcu.dtsi
new file mode 100644 (file)
index 0000000..d103824
--- /dev/null
+++ b/arch/arm/dts/k3-am62-mcu.dtsi
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+       mcu_pmx0: pinctrl@4084000 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x04084000 0x00 0x88>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0xffffffff>;
+       };
+
+       mcu_uart0: serial@4a00000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x04a00000 0x00 0x100>;
+               interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 149 0>;
+               clock-names = "fclk";
+       };
+
+       mcu_i2c0: i2c@4900000 {
+               compatible = "ti,am64-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x04900000 0x00 0x100>;
+               interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 106 2>;
+               clock-names = "fck";
+       };
+
+       mcu_spi0: spi@4b00000 {
+               compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+               reg = <0x00 0x04b00000 0x00 0x400>;
+               interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 147 0>;
+       };
+
+       mcu_spi1: spi@4b10000 {
+               compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+               reg = <0x00 0x04b10000 0x00 0x400>;
+               interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 148 0>;
+       };
+};

diff --git a/arch/arm/dts/k3-am62-wakeup.dtsi b/arch/arm/dts/k3-am62-wakeup.dtsi
new file mode 100644 (file)
index 0000000..4090134
--- /dev/null
+++ b/arch/arm/dts/k3-am62-wakeup.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_wakeup {
+       wkup_conf: syscon@43000000 {
+               compatible = "syscon", "simple-mfd";
+               reg = <0x00 0x43000000 0x00 0x20000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0x0 0x00 0x43000000 0x20000>;
+
+               chipid: chipid@14 {
+                       compatible = "ti,am654-chipid";
+                       reg = <0x14 0x4>;
+               };
+       };
+
+       wkup_uart0: serial@2b300000 {
+               compatible = "ti,am64-uart", "ti,am654-uart";
+               reg = <0x00 0x2b300000 0x00 0x100>;
+               interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+               power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 114 0>;
+               clock-names = "fclk";
+       };
+
+       wkup_i2c0: i2c@2b200000 {
+               compatible = "ti,am64-i2c", "ti,omap4-i2c";
+               reg = <0x00 0x02b200000 0x00 0x100>;
+               interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+               clocks = <&k3_clks 107 4>;
+               clock-names = "fck";
+       };
+};

diff --git a/arch/arm/dts/k3-am62.dtsi b/arch/arm/dts/k3-am62.dtsi
new file mode 100644 (file)
index 0000000..bc2997b
--- /dev/null
+++ b/arch/arm/dts/k3-am62.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM62 SoC Family
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+       model = "Texas Instruments K3 AM625 SoC";
+       compatible = "ti,am625";
+       interrupt-parent = <&gic500>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       chosen { };
+
+       firmware {
+               optee {
+                       compatible = "linaro,optee-tz";
+                       method = "smc";
+               };
+
+               psci: psci {
+                       compatible = "arm,psci-1.0";
+                       method = "smc";
+               };
+       };
+
+       a53_timer0: timer-cl0-cpu0 {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+       };
+
+       pmu: pmu {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       cbass_main: bus@f0000 {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+
+               ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
+                        <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
+                        <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+                        <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
+                        <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
+                        <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+                        <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
+                        <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+                        <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
+                        <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
+                        <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+                        <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
+                        <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */
+                        <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
+                        <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
+                        <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */
+                        <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
+                        <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+                        <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
+                        <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */
+                        <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+                        <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */
+                        <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
+                        <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+                        /* MCU Domain Range */
+                        <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
+
+                        /* Wakeup Domain Range */
+                        <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
+                        <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
+
+               cbass_mcu: bus@4000000 {
+                       compatible = "simple-bus";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
+               };
+
+               cbass_wakeup: bus@2b000000 {
+                       compatible = "simple-bus";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+                                <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
+               };
+       };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am62-main.dtsi"
+#include "k3-am62-mcu.dtsi"
+#include "k3-am62-wakeup.dtsi"

diff --git a/arch/arm/dts/k3-am625.dtsi b/arch/arm/dts/k3-am625.dtsi
new file mode 100644 (file)
index 0000000..887f31c
--- /dev/null
+++ b/arch/arm/dts/k3-am625.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM625 SoC family in Quad core configuration
+ *
+ * TRM: https://www.ti.com/lit/pdf/spruiv7
+ *
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am62.dtsi"
+
+/ {
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu-map {
+                       cluster0: cluster0 {
+                               core0 {
+                                       cpu = <&cpu0>;
+                               };
+
+                               core1 {
+                                       cpu = <&cpu1>;
+                               };
+
+                               core2 {
+                                       cpu = <&cpu2>;
+                               };
+
+                               core3 {
+                                       cpu = <&cpu3>;
+                               };
+                       };
+               };
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a53";
+                       reg = <0x000>;
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               cpu1: cpu@1 {
+                       compatible = "arm,cortex-a53";
+                       reg = <0x001>;
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               cpu2: cpu@2 {
+                       compatible = "arm,cortex-a53";
+                       reg = <0x002>;
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&L2_0>;
+               };
+
+               cpu3: cpu@3 {
+                       compatible = "arm,cortex-a53";
+                       reg = <0x003>;
+                       device_type = "cpu";
+                       enable-method = "psci";
+                       i-cache-size = <0x8000>;
+                       i-cache-line-size = <64>;
+                       i-cache-sets = <256>;
+                       d-cache-size = <0x8000>;
+                       d-cache-line-size = <64>;
+                       d-cache-sets = <128>;
+                       next-level-cache = <&L2_0>;
+               };
+       };
+
+       L2_0: l2-cache0 {
+               compatible = "cache";
+               cache-level = <2>;
+               cache-size = <0x40000>;
+               cache-line-size = <64>;
+               cache-sets = <512>;
+       };
+};