sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them

Our old hardcoded k and m values are based on PLL5 being configured in steps
of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the
DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i)
the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps.

This commit adjusts clock_set_pll5 to automatically select the best k and m
depending on the requested clk rate.

Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 193e31459cab828d493e9508c586576088ebc14d..ad50dd90f3f62d8a526f22f9029bb5157484108f 100644 (file)
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -148,13 +148,18 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 {
        struct sunxi_ccm_reg * const ccm =
                (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
-       const int k = 2;
-       const int m = 1;
+       const int max_n = 32;
+       int k = 1, m = 2;
 
        if (sigma_delta_enable)
                writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
 
        /* PLL5 rate = 24000000 * n * k / m */
+       if (clk > 24000000 * k * max_n / m) {
+               m = 1;
+               if (clk > 24000000 * k * max_n / m)
+                       k = 2;
+       }
        writel(CCM_PLL5_CTRL_EN |
               (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
               CCM_PLL5_CTRL_UPD |