dm: sunxi: Add support for serial using driver model

Add a driver for the designware serial UART used on sunxi. This just
redirects to the normal ns16550 driver.

Add a stdout-path to the device tree so that the correct UART is chosen.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts
index 046dfc0d45d8ebb21d8a7dd050fdb500dbbf6d35..f7cc8e7a09c2e5ece889bb364f47488eb9287bef 100644 (file)
--- a/arch/arm/dts/sun7i-a20-pcduino3.dts
+++ b/arch/arm/dts/sun7i-a20-pcduino3.dts
@@ -20,6 +20,10 @@
        model = "LinkSprite pcDuino3";
        compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
 
+       chosen {
+               stdout-path = &uart0;
+       };
+
        soc@01c00000 {
                mmc0: mmc@01c0f000 {
                        pinctrl-names = "default";

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 2c19ebc2885e90c77b58302e989527a162d9c517..8c8494276116360d5340d669c7e7e7130a6e1549 100644 (file)
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_UART) += altera_uart.o
 obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
+obj-$(CONFIG_DW_SERIAL) += serial_dw.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
 obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o

diff --git a/drivers/serial/serial_dw.c b/drivers/serial/serial_dw.c
new file mode 100644 (file)
index 0000000..a348f29
--- /dev/null
+++ b/drivers/serial/serial_dw.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id dw_serial_ids[] = {
+       { .compatible = "snps,dw-apb-uart" },
+       { }
+};
+
+static int dw_serial_ofdata_to_platdata(struct udevice *dev)
+{
+       struct ns16550_platdata *plat = dev_get_platdata(dev);
+       int ret;
+
+       ret = ns16550_serial_ofdata_to_platdata(dev);
+       if (ret)
+               return ret;
+       plat->clock = CONFIG_SYS_NS16550_CLK;
+
+       return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+       .name   = "serial_dw",
+       .id     = UCLASS_SERIAL,
+       .of_match = dw_serial_ids,
+       .ofdata_to_platdata = dw_serial_ofdata_to_platdata,
+       .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+       .priv_auto_alloc_size = sizeof(struct NS16550),
+       .probe = ns16550_serial_probe,
+       .ops    = &ns16550_serial_ops,
+};

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 316e7d93df4e394b5251a3a6ec5d540238f09dad..ce038eddf04b1858cc87bf22fc87709301559599 100644 (file)
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -30,6 +30,9 @@
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
 # define CONFIG_CMD_DM
 # define CONFIG_DM_GPIO
+# define CONFIG_DM_SERIAL
+# define CONFIG_DW_SERIAL
+# define CONFIG_SYS_MALLOC_F_LEN       (1 << 10)
 #endif
 
 /*
@@ -41,13 +44,15 @@
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 /* ns16550 reg in the low bits of cpu reg */
-#define CONFIG_SYS_NS16550_REG_SIZE    -4
 #define CONFIG_SYS_NS16550_CLK         24000000
-#define CONFIG_SYS_NS16550_COM1                SUNXI_UART0_BASE
-#define CONFIG_SYS_NS16550_COM2                SUNXI_UART1_BASE
-#define CONFIG_SYS_NS16550_COM3                SUNXI_UART2_BASE
-#define CONFIG_SYS_NS16550_COM4                SUNXI_UART3_BASE
-#define CONFIG_SYS_NS16550_COM5                SUNXI_R_UART_BASE
+#ifndef CONFIG_DM_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE   -4
+# define CONFIG_SYS_NS16550_COM1               SUNXI_UART0_BASE
+# define CONFIG_SYS_NS16550_COM2               SUNXI_UART1_BASE
+# define CONFIG_SYS_NS16550_COM3               SUNXI_UART2_BASE
+# define CONFIG_SYS_NS16550_COM4               SUNXI_UART3_BASE
+# define CONFIG_SYS_NS16550_COM5               SUNXI_R_UART_BASE
+#endif
 
 /* DRAM Base */
 #define CONFIG_SYS_SDRAM_BASE          0x40000000