Correct PPC Timebase register definitions (SPRN_TBRL...)

Patch by Stefan Roese, 07 Nov 2005

diff --git a/CHANGELOG b/CHANGELOG
index 9e8557083e908238a399cea67c6d3482bb420b66..df3003e4ca59499aa36a51fbcd5b93be83b85ea3 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Correct PPC Timebase register definitions (SPRN_TBRL...)
+  Patch by Stefan Roese, 07 Nov 2005
+
 * Adjust bd->bi_flashstart on Yellowstone & Yosemite to correct size
   Patch by Stefan Roese, 05 Nov 2005
 

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 551da35294e3c6d68a847eb36aba239d42736dbd..0b30d2d71085bffe882d9ffdab52963397b2b861 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -310,10 +310,10 @@
 #define SPRN_TBHU      0x3CC   /* Time Base High User-mode */
 #define SPRN_TBLO      0x3DD   /* Time Base Low */
 #define SPRN_TBLU      0x3CD   /* Time Base Low User-mode */
-#define SPRN_TBRL      0x10D   /* Time Base Read Lower Register */
-#define SPRN_TBRU      0x10C   /* Time Base Read Upper Register */
-#define SPRN_TBWL      0x11D   /* Time Base Write Lower Register */
-#define SPRN_TBWU      0x11C   /* Time Base Write Upper Register */
+#define SPRN_TBRL      0x10C   /* Time Base Read Lower Register */
+#define SPRN_TBRU      0x10D   /* Time Base Read Upper Register */
+#define SPRN_TBWL      0x11C   /* Time Base Write Lower Register */
+#define SPRN_TBWU      0x11D   /* Time Base Write Upper Register */
 #ifndef CONFIG_BOOKE
 #define SPRN_TCR       0x3DA   /* Timer Control Register */
 #else