]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
configs: ls1028a: use default SDHC clock divider value
authorYangbo Lu <yangbo.lu@nxp.com>
Thu, 16 Jan 2020 05:19:44 +0000 (13:19 +0800)
committerPeng Fan <peng.fan@nxp.com>
Thu, 16 Jan 2020 05:19:44 +0000 (13:19 +0800)
The SDHC clock divider value for LS1028A should be default 2,
not 1.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
configs/ls1028aqds_tfa_defconfig
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
configs/ls1028ardb_tfa_defconfig

index 31e3b5a9b63ce98af54ef59f339c9ebc702b2172..c80f8c7699ffa7c7ac81d2c565f1993fb4e858be 100644 (file)
@@ -4,7 +4,6 @@ CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_NXP_ESBC=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
-CONFIG_SYS_FSL_SDHC_CLK_DIV=1
 CONFIG_ENV_SIZE=0x2000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
index 72922120e9b87640404feb71fbc4c3e65b93f781..b3e3bcfe63e6ef4947e5e80464b0b6565bd70ff0 100644 (file)
@@ -3,7 +3,6 @@ CONFIG_TARGET_LS1028AQDS=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_FSPI_AHB_EN_4BYTE=y
-CONFIG_SYS_FSL_SDHC_CLK_DIV=1
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x500000
 CONFIG_NR_DRAM_BANKS=2
index db92204d988853353e9d40b9447c3e9c6bae74b1..02770b1064bd100ff42ae7c1b4007f82ee3ff84b 100644 (file)
@@ -4,7 +4,6 @@ CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_NXP_ESBC=y
 CONFIG_FSPI_AHB_EN_4BYTE=y
-CONFIG_SYS_FSL_SDHC_CLK_DIV=1
 CONFIG_ENV_SIZE=0x2000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
index 41fe40a853dc1e2f964a801d2a7446faa4054902..6715d310fa5f8ac5a0d5b208e9be1bd8202103e6 100644 (file)
@@ -3,7 +3,6 @@ CONFIG_TARGET_LS1028ARDB=y
 CONFIG_TFABOOT=y
 CONFIG_SYS_MALLOC_F_LEN=0x6000
 CONFIG_FSPI_AHB_EN_4BYTE=y
-CONFIG_SYS_FSL_SDHC_CLK_DIV=1
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0x500000
 CONFIG_NR_DRAM_BANKS=2