sunxi: enable dual rank detection in DesignWare-like DRAM code

The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second rank.

Set the default value to dual rank, thus the rank detection code can
work and finally the rank setting will be the correct value.

Currently we know little about the dual-rank on R40, and the usage
of A15 address line seems to be breaking dual-rank support. The only R40
board currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather
than dual-rank, thus we cannot do research for it. So dual rank detection
is temporarily disabled on R40.

This change is tested on a Orange Pi One (H3, single rank), a Pine64+
2GiB version (A64, single rank) , a Pinebook early prototype with DDR3
(A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins
on one chip).

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index a5706423cbe10c0c6d2bc56d5f74d1d07e06548c..bd606ccc659f2491b70f1d10dc60021bc9846071 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -686,7 +686,7 @@ unsigned long sunxi_dram_init(void)
                        (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 
        struct dram_para para = {
-               .dual_rank = 0,
+               .dual_rank = 1,
                .bus_full_width = 1,
                .row_bits = 15,
                .bank_bits = 3,
@@ -719,6 +719,8 @@ unsigned long sunxi_dram_init(void)
        uint16_t socid = SOCID_H3;
 #elif defined(CONFIG_MACH_SUN8I_R40)
        uint16_t socid = SOCID_R40;
+       /* Currently we cannot support R40 with dual rank memory */
+       para.dual_rank = 0;
 #elif defined(CONFIG_MACH_SUN50I)
        uint16_t socid = SOCID_A64;
 #elif defined(CONFIG_MACH_SUN50I_H5)