armv8: Add workaround for USB erratum A-009007

Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values.

Program register USB_PHY_RX_OVRD_IN_HI in certain sequence
to make the Rx compliance test pass.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
[YS: Reordered Kconfig options]
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index b6410d731fbee20daab0bd513955a3f3f6e2e275..3518d8601d176b0e8e0782973d4deced6c17433a 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -17,6 +17,7 @@ config ARCH_LS1043A
        select SYS_FSL_DDR_VER_50
        select SYS_FSL_ERRATUM_A008850
        select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
        select SYS_FSL_ERRATUM_A009008
        select SYS_FSL_ERRATUM_A009660
        select SYS_FSL_ERRATUM_A009663
@@ -43,6 +44,7 @@ config ARCH_LS1046A
        select SYS_FSL_ERRATUM_A008511
        select SYS_FSL_ERRATUM_A008850
        select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
        select SYS_FSL_ERRATUM_A009008
        select SYS_FSL_ERRATUM_A009798
        select SYS_FSL_ERRATUM_A009801
@@ -107,6 +109,7 @@ config ARCH_LS2080A
        select SYS_FSL_ERRATUM_A008514
        select SYS_FSL_ERRATUM_A008585
        select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
        select SYS_FSL_ERRATUM_A009008
        select SYS_FSL_ERRATUM_A009635
        select SYS_FSL_ERRATUM_A009663
@@ -260,6 +263,11 @@ endmenu
 config SYS_FSL_ERRATUM_A008997
        bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+       bool
+       help
+         Workaround for USB PHY erratum A009007
+
 config SYS_FSL_ERRATUM_A009008
        bool "Workaround for USB PHY erratum A009008"
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c7180f1ebe3171bbee3a70f4d687fdad2984a186..6698c0467d7c0240f2711b14457b2a7088668367 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -119,6 +119,44 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+
+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)     \
+       out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);      \
+       out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);      \
+       out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);      \
+       out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+
+#elif defined(CONFIG_ARCH_LS2080A)
+
+#define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy)     \
+       out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
+       out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
+       out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
+       out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
+
+#endif
+
+static void erratum_a009007(void)
+{
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+       void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
+
+       PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+
+       usb_phy = (void __iomem *)SCFG_USB_PHY2;
+       PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+
+       usb_phy = (void __iomem *)SCFG_USB_PHY3;
+       PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
+#elif defined(CONFIG_ARCH_LS2080A)
+       void __iomem *dcsr = (void __iomem *)DCSR_BASE;
+
+       PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
+       PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -268,6 +306,7 @@ void fsl_lsch3_early_init_f(void)
        erratum_a009008();
        erratum_a009798();
        erratum_a008997();
+       erratum_a009007();
 #ifdef CONFIG_CHAIN_OF_TRUST
        /* In case of Secure Boot, the IBR configures the SMMU
        * to allow only Secure transactions.
@@ -549,6 +588,7 @@ void fsl_lsch2_early_init_f(void)
        erratum_a009008();
        erratum_a009798();
        erratum_a008997();
+       erratum_a009007();
 }
 #endif
 

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index ebb99a8e2cba27f95968b0b8bc66ebeae3175b46..2561ead7c392eccab98016e5aefce550290f5e18 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -347,6 +347,14 @@ struct ccsr_gur {
 #define SCFG_USB_TXVREFTUNE                    0x9
 #define SCFG_USB_SQRXTUNE_MASK         0x7
 #define SCFG_USB_PCSTXSWINGFULL                0x47
+#define SCFG_USB_PHY1                  0x084F0000
+#define SCFG_USB_PHY2                  0x08500000
+#define SCFG_USB_PHY3                  0x08510000
+#define SCFG_USB_PHY_RX_OVRD_IN_HI             0x200c
+#define USB_PHY_RX_EQ_VAL_1            0x0000
+#define USB_PHY_RX_EQ_VAL_2            0x0080
+#define USB_PHY_RX_EQ_VAL_3            0x0380
+#define USB_PHY_RX_EQ_VAL_4            0x0b80
 
 #define SCFG_SNPCNFGCR_SECRDSNP                0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP                0x40000000

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3c91e69bd9011d218bf729d0ccdfb2d03f43a15a..6c74ee05d16ad77b51f58a6acd08cabd1713e5e6 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -137,6 +137,15 @@
 #define SCFG_USB_SQRXTUNE_MASK 0x7
 #define SCFG_QSPICLKCTLR       0x10
 
+#define DCSR_BASE              0x700000000ULL
+#define DCSR_USB_PHY1                  0x4600000
+#define DCSR_USB_PHY2                  0x4610000
+#define DCSR_USB_PHY_RX_OVRD_IN_HI     0x200C
+#define USB_PHY_RX_EQ_VAL_1            0x0000
+#define USB_PHY_RX_EQ_VAL_2            0x0080
+#define USB_PHY_RX_EQ_VAL_3            0x0380
+#define USB_PHY_RX_EQ_VAL_4            0x0b80
+
 #define TP_ITYP_AV             0x00000001      /* Initiator available */
 #define TP_ITYP_TYPE(x)        (((x) & 0x6) >> 1)      /* Initiator Type */
 #define TP_ITYP_TYPE_ARM       0x0