Changes for U-Boot 1.0.2:
======================================================================
+* Patch by Pierre Aubert, 26 Feb 2004
+ add IDE support for MPC5200
+
+* Patch by Masami Komiya, 26 Feb 2004:
+ add autoload via NFS
+
+* Patch by Stephen Williams
+ Use of CONFIG_SERIAL_SOFTWARE_FIFO in board.c consistent with uses
+ elsewhere in the source.
+
* Patch by Steven Scholz, 25 Feb 2004:
- Timeouts in FPGA code should be based on CFG_HZ
- Minor cleanup in code for Altera FPGA ACEX1K
* Patch by Markus Pietrek, 24 Feb 2004:
NS9750 DevBoard added
-* Patch by Pierre AUBERT, 24 Feb 2004
+* Patch by Pierre Aubert, 24 Feb 2004
add USB support for MPC5200
* Patch by Steven Scholz, 24 Feb 2004:
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
- *
+ *
***********************************************************************/
#ifdef CONFIG_STATUS_LED
#ifdef CONFIG_8xx
# include <mpc8xx.h>
#endif
+#ifdef CONFIG_MPC5xxx
+#include <mpc5xxx.h>
+#endif
#include <ide.h>
#include <ata.h>
#ifdef CONFIG_STATUS_LED
START = start.o
ASOBJS = io.o firmware_sc_task_bestcomm.impl.o firmware_sc_task.impl.o
-OBJS = i2c.o traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o \
- loadtask.o fec.o pci_mpc5200.o usb_ohci.o
+OBJS = i2c.o traps.o cpu.o cpu_init.o fec.o ide.o interrupts.o \
+ loadtask.o pci_mpc5200.o serial.o speed.o usb_ohci.o
all: .depend $(START) $(ASOBJS) $(LIB)
--- /dev/null
+/*
+ * (C) Copyright 2004
+ * Pierre AUBERT, Staubli Faverges, <p.aubert@staubli.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Init is derived from Linux code.
+ */
+#include <common.h>
+
+#ifdef CFG_CMD_IDE
+#include <mpc5xxx.h>
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+#define GPIO_PSC1_4 0x01000000ul
+
+int ide_preinit (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ long period, t0, t1, t2_8, t2_16, t4, ta;
+ vu_long reg;
+ struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
+
+ reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
+ reg = (reg & ~0x03000000ul) | 0x01000000ul;
+ *(vu_long *) MPC5XXX_GPS_PORT_CONFIG = reg;
+
+ /* All sample codes do that... */
+ *(vu_long *) MPC5XXX_ATA_SHARE_COUNT = 0;
+
+ /* Configure and reset host */
+ *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY |
+ MPC5xxx_ATA_HOSTCONF_SMR | MPC5xxx_ATA_HOSTCONF_FR;
+ udelay (10);
+ *(vu_long *) MPC5XXX_ATA_HOST_CONFIG = MPC5xxx_ATA_HOSTCONF_IORDY;
+
+ /* Disable prefetch on Commbus */
+ psdma->PtdCntrl |= 1;
+
+ /* Init timings : we use PIO mode 0 timings */
+ period = 1000000000 / gd->ipb_clk; /* period in ns */
+
+ t0 = CALC_TIMING (600);
+ t2_8 = CALC_TIMING (290);
+ t2_16 = CALC_TIMING (165);
+ reg = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8);
+ *(vu_long *) MPC5XXX_ATA_PIO1 = reg;
+
+ t4 = CALC_TIMING (30);
+ t1 = CALC_TIMING (70);
+ ta = CALC_TIMING (35);
+ reg = (t4 << 24) | (t1 << 16) | (ta << 8);
+
+ *(vu_long *) MPC5XXX_ATA_PIO2 = reg;
+
+#if defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET)
+ /* Configure PSC1_4 as GPIO output for ATA reset */
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+ *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+#endif /* defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET) */
+
+ return (0);
+}
+
+#if defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET)
+void ide_set_reset (int idereset)
+{
+ if (idereset) {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+ } else {
+ *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
+ }
+}
+#endif /* defined (CONFIG_ICECUBE) && defined (CONFIG_IDE_RESET) */
+#endif /* CFG_CMD_IDE */
#endif
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
/* USB */
#if 1
#define CONFIG_USB_OHCI
/*
* Supported commands
*/
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD | \
- CFG_CMD_I2C | CFG_CMD_EEPROM | \
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_FAT | \
+ CFG_CMD_I2C | \
+ CFG_CMD_IDE | \
+ ADD_PCI_CMD | \
ADD_USB_CMD)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CFG_RESET_ADDRESS 0xff000000
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+
+#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+#undef CONFIG_IDE_LED /* LED for ide not supported */
+
+#define CONFIG_IDE_RESET /* reset for ide supported */
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
+
+#define CFG_ATA_IDE0_OFFSET 0x0000
+
+#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+
+/* Offset for data I/O */
+#define CFG_ATA_DATA_OFFSET (0x0060)
+
+/* Offset for normal register accesses */
+#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers */
+#define CFG_ATA_ALT_OFFSET (0x005c)
+
+/* Interval between registers */
+#define CFG_ATA_STRIDE 4
+
#endif /* __CONFIG_H */
#error #### Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
/* older kernels need clock in MHz newer in Hz */
- /* #define CONFIG_CLOCKS_IN_MHZ 1 *//* clocks passsed to Linux in MHz */
+ /* #define CONFIG_CLOCKS_IN_MHZ 1 */ /* clocks passsed to Linux in MHz */
#undef CONFIG_CLOCKS_IN_MHZ
#define CONFIG_BOOTDELAY 10
- /*#define CONFIG_DRAM_SPEED 66 *//* MHz */
+ /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_FLASH | \
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2 /* for MPC8240 only */
- /*#define CONFIG_133MHZ_DRAM 1 *//* For 133 MHZ DRAM only !!!!!!!!!!! */
+ /*#define CONFIG_133MHZ_DRAM 1 */ /* For 133 MHZ DRAM only !!!!!!!!!!! */
#if defined (CONFIG_MPC8245)
/* Bit-field values for PMCR2. */
#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
+#define MPC5XXX_WU_GPIO (CFG_MBAR + 0x0c00)
#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
#define MPC5XXX_USB (CFG_MBAR + 0x1000)
#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
#endif
#define MPC5XXX_FEC (CFG_MBAR + 0x3000)
+#define MPC5XXX_ATA (CFG_MBAR + 0x3A00)
#define MPC5XXX_I2C1 (CFG_MBAR + 0x3D00)
#define MPC5XXX_I2C2 (CFG_MBAR + 0x3D40)
/* GPIO registers */
#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000)
+/* WakeUp GPIO registers */
+#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000)
+#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004)
+#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008)
+#define MPC5XXX_WU_GPIO_DATA (MPC5XXX_WU_GPIO + 0x000c)
+
/* PCI registers */
#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04)
#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c)
#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
+/* ATA registers */
+#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000)
+#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008)
+#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C)
+#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C)
+
/* I2Cn control register bits */
#define I2C_EN 0x80
#define I2C_IEN 0x40
#define PSC_MODE_ONE_STOP 0x07
#define PSC_MODE_TWO_STOP 0x0f
+/* ATA config fields */
+#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine
+ reset */
+#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
+#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt
+ in PIO */
+#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports
+ IORDY protocol */
+
#ifndef __ASSEMBLY__
struct mpc5xxx_psc {
volatile u8 mode; /* PSC + 0x00 */
/* Must happen after interrupts are initialized since
* an irq handler gets installed
*/
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+#if CONFIG_SERIAL_SOFTWARE_FIFO
serial_buffered_init();
#endif
*/
timer_init();
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+#if CONFIG_SERIAL_SOFTWARE_FIFO
serial_buffered_init();
#endif
/* Must happen after interrupts are initialized since
* an irq handler gets installed
*/
-#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
+#if CONFIG_SERIAL_SOFTWARE_FIFO
serial_buffered_init();
#endif
debug ("Got good BOOTP\n");
- if (((s = getenv("autoload")) != NULL) && (*s == 'n')) {
- /*
- * Just use BOOTP to configure system;
- * Do not use TFTP to load the bootfile.
- */
- NetState = NETLOOP_SUCCESS;
- return;
+ if ((s = getenv("autoload")) != NULL) {
+ if (*s == 'n') {
+ /*
+ * Just use BOOTP to configure system;
+ * Do not use TFTP to load the bootfile.
+ */
+ NetState = NETLOOP_SUCCESS;
+ return;
+ } else if (strcmp(s, "NFS") == 0) {
+ /*
+ * Use NFS to load the bootfile.
+ */
+ NfsStart();
+ return;
+ }
}
TftpStart();
printf("\n");
/* Obey the 'autoload' setting */
- if (((s = getenv("autoload")) != NULL) && (*s == 'n')) {
- NetState = NETLOOP_SUCCESS;
- return;
+ if ((s = getenv("autoload")) != NULL) {
+ if (*s == 'n') {
+ /*
+ * Just use BOOTP to configure system;
+ * Do not use TFTP to load the bootfile.
+ */
+ NetState = NETLOOP_SUCCESS;
+ return;
+ } else if (strcmp(s, "NFS") == 0) {
+ /*
+ * Use NFS to load the bootfile.
+ */
+ NfsStart();
+ return;
+ }
}
TftpStart();
return;
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