*/
#ifndef _CLOCKS_OMAP4_H_
#define _CLOCKS_OMAP4_H_
-#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
*/
#ifndef _CLOCKS_OMAP5_H_
#define _CLOCKS_OMAP5_H_
-#include <asm/omap_common.h>
/*
* Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
#include <linux/types.h>
#define NUM_SYS_CLKS 7
+#define SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
struct bd_info;
#include <asm/arch/sata.h>
#include <sata.h>
#include <asm/io.h>
+#include <asm/omap_common.h>
#include "pipe3-phy.h"
static struct pipe3_dpll_map dpll_map_sata[] = {
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clock.h>
+#include <asm/omap_common.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
* Nothing really to do with interrupts, just starts up a counter.
*/
-#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
+#define TIMER_CLOCK (V_SCLK / (2 << SYS_PTV))
#define TIMER_OVERFLOW_VAL 0xffffffff
#define TIMER_LOAD_VAL 0
/* start the counter ticking up, reload value on overflow */
writel(TIMER_LOAD_VAL, &timer_base->tldr);
/* enable timer */
- writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
+ writel((SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
&timer_base->tclr);
return 0;
#include <timer.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/omap_common.h>
#include <linux/bitops.h>
/* Timer register bits */
if (!uc_priv->clock_rate)
uc_priv->clock_rate = V_SCLK;
- uc_priv->clock_rate /= (2 << CONFIG_SYS_PTV);
+ uc_priv->clock_rate /= (2 << SYS_PTV);
/* start the counter ticking up, reload value on overflow */
writel(0, &priv->regs->tldr);
writel(0, &priv->regs->tcrr);
/* enable timer */
- writel((CONFIG_SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
+ writel((SYS_PTV << 2) | TCLR_PRE_EN | TCLR_AUTO_RELOAD |
TCLR_START, &priv->regs->tclr);
return 0;
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#include <asm/arch/omap.h>
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/*
* Physical Memory Map
GENERATED_GBL_DATA_SIZE)
/* Platform/Board specific defs */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_SERIAL
*/
#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
-#define CONFIG_SYS_PTV 2
#define V_NS16550_CLK 48000000
#define V_OSCK 26000000
* Platform/Board specific defs
*/
#define CONFIG_SYS_TIMERBASE 0x4802E000
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_SERIAL
* Platform/Board specific defs
*/
#define CONFIG_SYS_TIMERBASE 0x4802E000
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/*
* NS16550 Configuration
GENERATED_GBL_DATA_SIZE)
#endif
-/* Timer information. */
-#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
-
/* If DM_I2C, enable non-DM I2C support */
/*