imx8m: lock id_swap_bypass bit in tzc380 enable

According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock
bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in
order to avoid AXI bus errors when GPU is enabled on the platform.
TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable
derivatives, but is missing a lock settings to be applied.

Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have
it implemented.

Since we're here, provide also names to bits from TRM instead of using
BIT() macro in the code.

Fixes: deca6cfbf5d7 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors")
Fixes: a07c7181296f ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Peng Fan <peng.fan@nxp.com>

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b800da13a1e489ca1d7212de8f94d56a259e4414..45d95a7c1973cf911cff4dab02e27f86e4f0b681 100644 (file)
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -80,8 +80,10 @@
 #include <linux/bitops.h>
 #include <stdbool.h>
 
-#define GPR_TZASC_EN           BIT(0)
-#define GPR_TZASC_EN_LOCK      BIT(16)
+#define GPR_TZASC_EN                                   BIT(0)
+#define GPR_TZASC_ID_SWAP_BYPASS               BIT(1)
+#define GPR_TZASC_EN_LOCK                              BIT(16)
+#define GPR_TZASC_ID_SWAP_BYPASS_LOCK  BIT(17)
 
 #define SRC_SCR_M4_ENABLE_OFFSET       3
 #define SRC_SCR_M4_ENABLE_MASK         BIT(3)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 0c6e903629fd2915d75db5d8b29116a24703678d..da106769b112aab5557d6e172e41c9e591658301 100644 (file)
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -66,8 +66,21 @@ void enable_tzc380(void)
        /* Enable TZASC and lock setting */
        setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
        setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
+
+       /*
+        * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
+        * order to avoid AXI Bus errors when GPU is in use
+        */
        if (is_imx8mm() || is_imx8mn() || is_imx8mp())
-               setbits_le32(&gpr->gpr[10], BIT(1));
+               setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
+
+       /*
+        * imx8mn and imx8mp implements the lock bit for
+        * TZASC_ID_SWAP_BYPASS, enable it to lock settings
+        */
+       if (is_imx8mn() || is_imx8mp())
+               setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
+
        /*
         * set Region 0 attribute to allow secure and non-secure
         * read/write permission. Found some masters like usb dwc3