Revert "spi: add config option to enable the WP pin function on st micron flashes"

This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.

Note: Even un-reverting this patch couldn't works as expected, based
on the latest testing from Heiko Schocher.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Cc: Heiko Schocher <hs@denx.de>

diff --git a/README b/README
index fc1fd52f53053268fe3bdb4d7040dffc855a53f4..82224f75e4964a21d92a425eb12e9de6508b5a5a 100644 (file)
--- a/README
+++ b/README
@@ -3086,17 +3086,6 @@ CBFS (Coreboot Filesystem) support
                memories can be connected with a given cs line.
                Currently Xilinx Zynq qspi supports these type of connections.
 
-               CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-               enable the W#/Vpp signal to disable writing to the status
-               register on ST MICRON flashes like the N25Q128.
-               The status register write enable/disable bit, combined with
-               the W#/VPP signal provides hardware data protection for the
-               device as follows: When the enable/disable bit is set to 1,
-               and the W#/VPP signal is driven LOW, the status register
-               nonvolatile bits become read-only and the WRITE STATUS REGISTER
-               operation will not execute. The only way to exit this
-               hardware-protected mode is to drive W#/VPP HIGH.
-
 - SystemACE Support:
                CONFIG_SYSTEMACE
 

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 785f7a96fed28d8d7cb8297fa009705e183c9290..bd834dc26325bbb838d7333362cf1225d88e2447 100644 (file)
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -97,10 +97,6 @@ enum {
 #define STATUS_QEB_MXIC                (1 << 6)
 #define STATUS_PEC                     (1 << 7)
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD                    (1 << 7) /* SR write protect */
-#endif
-
 /* Flash timeout values */
 #define SPI_FLASH_PROG_TIMEOUT         (2 * CONFIG_SYS_HZ)
 #define SPI_FLASH_PAGE_ERASE_TIMEOUT           (5 * CONFIG_SYS_HZ)

diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 2ee228d3f3cb97ad53450b907760c5bd66252c40..de8d0b7f7cbdf786f50c1ca37189a9b0edc78be1 100644 (file)
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -288,34 +288,6 @@ int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 }
 #endif /* CONFIG_OF_CONTROL */
 
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       u8 status;
-       int ret;
-
-       ret = spi_flash_cmd_read_status(flash, &status);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
-       if (ret < 0)
-               return ret;
-
-       ret = spi_flash_cmd_write_disable(flash);
-       if (ret < 0)
-               return ret;
-
-       return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
-       return 0;
-}
-#endif
-
 /**
  * spi_flash_probe_slave() - Probe for a SPI flash device on a bus
  *
@@ -394,8 +366,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
                puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
        }
 #endif
-       if (spi_enable_wp_pin(flash))
-               puts("Enable WP pin failed\n");
 
        /* Release spi bus */
        spi_release_bus(spi);