]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106
authorMichal Simek <michal.simek@xilinx.com>
Wed, 11 May 2022 09:52:54 +0000 (11:52 +0200)
committerMichal Simek <michal.simek@amd.com>
Wed, 18 May 2022 11:17:54 +0000 (13:17 +0200)
Origin DT binding just specify driver but wasn't aligned with DT binding
which came later. Extend description for zcu102 and zcu106 to cover latest
binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/db66a4bb501183ffbd033da4dd263afdb214f8ec.1652262769.git.michal.simek@amd.com
arch/arm/dts/zynqmp-zcu102-revA.dts
arch/arm/dts/zynqmp-zcu106-revA.dts

index aac798d6e74ae35342b352c78cbde6d1f65f47e0..c13b52a6aeaac0c88aac6b862593b09645407a05 100644 (file)
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <4>;
-                       /* SI5328 - u20 */
+                       si5328: clock-generator@69 {/* SI5328 - u20 */
+                               compatible = "silabs,si5328";
+                               reg = <0x69>;
+                               /*
+                                * Chip has interrupt present connected to PL
+                                * interrupt-parent = <&>;
+                                * interrupts = <>;
+                                */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               #clock-cells = <1>;
+                               clocks = <&refhdmi>;
+                               clock-names = "xtal";
+                               clock-output-names = "si5328";
+
+                               si5328_clk: clk0@0 {
+                                       reg = <0>;
+                                       clock-frequency = <27000000>;
+                               };
+                       };
                };
                /* 5 - 7 unconnected */
        };
index 03624648cd7135618350eed8552039923c943a55..6dfc8fe17bf218ae2501d75b55f8c9d9fa4f87f1 100644 (file)
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <4>;
-                       /* SI5328 - u20 */
+                       si5328: clock-generator@69 {/* SI5328 - u20 */
+                               compatible = "silabs,si5328";
+                               reg = <0x69>;
+                               /*
+                                * Chip has interrupt present connected to PL
+                                * interrupt-parent = <&>;
+                                * interrupts = <>;
+                                */
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               #clock-cells = <1>;
+                               clocks = <&refhdmi>;
+                               clock-names = "xtal";
+                               clock-output-names = "si5328";
+
+                               si5328_clk: clk0@0 {
+                                       reg = <0>;
+                                       clock-frequency = <27000000>;
+                               };
+                       };
                };
                i2c@5 {
                        #address-cells = <1>;