vmImage: $(ubuntu_vm)
strategy:
# Use almost the same target division in .travis.yml, only merged
- # 4 small build jobs (arc/microblaze/nds32/xtensa) into one.
+ # 3 small build jobs (arc/microblaze/xtensa) into one.
matrix:
- arc_microblaze_nds32_xtensa:
- BUILDMAN: "arc microblaze nds32 xtensa"
+ arc_microblaze_xtensa:
+ BUILDMAN: "arc microblaze xtensa"
arm11_arm7_arm920t_arm946es:
BUILDMAN: "arm11 arm7 arm920t arm946es"
arm926ejs:
T: git https://source.denx.de/u-boot/custodians/u-boot-nand-flash.git
F: drivers/mtd/nand/raw/
-NDS32
-M: Rick Chen <rick@andestech.com>
-S: Maintained
-T: git https://source.denx.de/u-boot/custodians/u-boot-nds32.git
-F: arch/nds32/
-
NETWORK
M: Joe Hershberger <joe.hershberger@ni.com>
M: Ramon Fried <rfried.dev@gmail.com>
/m68k Files generic to m68k architecture
/microblaze Files generic to microblaze architecture
/mips Files generic to MIPS architecture
- /nds32 Files generic to NDS32 architecture
/nios2 Files generic to Altera NIOS2 architecture
/powerpc Files generic to PowerPC architecture
/riscv Files generic to RISC-V architecture
LynxOS, pSOS, QNX, RTEMS, INTEGRITY;
Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, INTEGRITY).
* Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
- IA64, MIPS, NDS32, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
- Currently supported: ARM, Intel x86, MIPS, NDS32, Nios II, PowerPC).
+ IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
+ Currently supported: ARM, Intel x86, MIPS, Nios II, PowerPC).
* Compression Type (uncompressed, gzip, bzip2)
* Load Address
* Entry Point
Note: on Nios II, we give "-G0" option to gcc and don't use gp
to access small data sections, so gp is free.
-On NDS32, the following registers are used:
-
- R0-R1: argument/return
- R2-R5: argument
- R15: temporary register for assembler
- R16: trampoline register
- R28: frame pointer (FP)
- R29: global pointer (GP)
- R30: link register (LP)
- R31: stack pointer (SP)
- PC: program counter (PC)
-
- ==> U-Boot will use R10 to hold a pointer to the global data
-
-NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope,
-or current versions of GCC may "optimize" the code too much.
-
On RISC-V, the following registers are used:
x0: hard-wired zero (zero)
config ARCH_MAP_SYSMEM
- depends on SANDBOX || NDS32
+ depends on SANDBOX
def_bool y
config CREATE_ARCH_SYMLINK
select SUPPORT_OF_CONTROL
select SPL_SEPARATE_BSS if SPL
-config NDS32
- bool "NDS32 architecture"
- select SUPPORT_OF_CONTROL
-
config NIOS2
bool "Nios II architecture"
select CPU
config SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
- depends on ARM || NDS32 || MIPS || RISCV
+ depends on ARM || MIPS || RISCV
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
config SPL_SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
- depends on SPL && (ARM || NDS32 || MIPS || RISCV)
+ depends on SPL && (ARM || MIPS || RISCV)
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
source "arch/m68k/Kconfig"
source "arch/microblaze/Kconfig"
source "arch/mips/Kconfig"
-source "arch/nds32/Kconfig"
source "arch/nios2/Kconfig"
source "arch/powerpc/Kconfig"
source "arch/sandbox/Kconfig"
+++ /dev/null
-menu "NDS32 architecture"
- depends on NDS32
-
-config SYS_ARCH
- default "nds32"
-
-choice
- prompt "Target select"
- optional
-
-config TARGET_ADP_AG101P
- bool "Support adp-ag101p"
-
-config TARGET_ADP_AE3XX
- bool "Support adp-ae3xx"
-
-endchoice
-
-config SYS_ICACHE_OFF
- bool "Do not enable icache"
- help
- Do not enable instruction cache in U-Boot.
-
-config SPL_SYS_ICACHE_OFF
- bool "Do not enable icache in SPL"
- depends on SPL
- default SYS_ICACHE_OFF
- help
- Do not enable instruction cache in SPL.
-
-config SYS_DCACHE_OFF
- bool "Do not enable dcache"
- help
- Do not enable data cache in U-Boot.
-
-config SPL_SYS_DCACHE_OFF
- bool "Do not enable dcache in SPL"
- depends on SPL
- default SYS_DCACHE_OFF
- help
- Do not enable data cache in SPL.
-
-source "board/AndesTech/adp-ag101p/Kconfig"
-source "board/AndesTech/adp-ae3xx/Kconfig"
-
-endmenu
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-
-head-y := arch/nds32/cpu/$(CPU)/start.o
-
-libs-y += arch/nds32/cpu/$(CPU)/
-libs-y += arch/nds32/lib/
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2011
-# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
-# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
-#
-
-CONFIG_STANDALONE_LOAD_ADDR = 0x300000
-LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/nds32.lds
-
-PLATFORM_RELFLAGS += -fno-common -mrelax -mno-ext-fpu-dp -mfloat-abi=soft
-PLATFORM_RELFLAGS += -gdwarf-2
-PLATFORM_CPPFLAGS += -D__nds32__ -ffixed-10 -fpie -mcmodel=large
-
-LDFLAGS_u-boot = --gc-sections --relax -pie --mabi=AABI
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2011 Andes Technology Corporation
-# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
-# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
-
-extra-y = start.o
-
-obj-$(if $(filter ag101,$(SOC)),y) += ag101/
-obj-$(if $(filter ae3xx,$(SOC)),y) += ae3xx/
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# Copyright (C) 2011 Andes Technology Corporation
-# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
-# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
-
-obj-y := cpu.o timer.o
-obj-y += lowlevel_init.o
-
-ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
-obj-y += watchdog.o
-endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-/* CPU specific code */
-#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
-#include <irq_func.h>
-#include <watchdog.h>
-#include <asm/cache.h>
-
-#include <faraday/ftwdt010_wdt.h>
-
-/*
- * cleanup_before_linux() is called just before we call linux
- * it prepares the processor for linux
- *
- * we disable interrupt and caches.
- */
-int cleanup_before_linux(void)
-{
- disable_interrupts();
-
- /* turn off I/D-cache */
- cache_flush();
- icache_disable();
- dcache_disable();
- return 0;
-}
-
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- disable_interrupts();
- panic("AE3XX wdt not support yet.\n");
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-.pic
-
-.text
-
-#include <common.h>
-#include <config.h>
-
-#include <asm/macro.h>
-#include <generated/asm-offsets.h>
-
-/*
- * parameters for the SDRAM controller
- */
-#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
-#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
-#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
-#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
-#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
-#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
-
-#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
-#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
-#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
-#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
-
-#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
-#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
-
-
-/*
- * for Orca and Emerald
- */
-#define BOARD_ID_REG 0x104
-#define BOARD_ID_FAMILY_MASK 0xfff000
-#define BOARD_ID_FAMILY_V5 0x556000
-#define BOARD_ID_FAMILY_K7 0x74b000
-
-/*
- * parameters for the static memory controller
- */
-#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
-#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
-
-#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
-#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
-
-/*
- * for Orca and Emerald
- */
-#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
-#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
-
-/*
- * parameters for the pmu controoler
- */
-#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
-
-/*
- * numeric 7 segment display
- */
-.macro led, num
- write32 CONFIG_DEBUG_LED, \num
-.endm
-
-/*
- * Waiting for SDRAM to set up
- */
-.macro wait_sdram
- li $r0, CONFIG_FTSDMC021_BASE
-1:
- lwi $r1, [$r0+FTSDMC021_CR2]
- bnez $r1, 1b
-.endm
-
-.globl mem_init
-mem_init:
- move $r11, $lp
- li $r0, SMC_BANK0_CR_A
- lwi $r1, [$r0+#0x00]
- ori $r1, $r1, 0x8f0
- xori $r1, $r1, 0x8f0
- /* 16-bit mode */
- ori $r1, $r1, 0x60
- li $r2, 0x00153153
- swi $r1, [$r0+#0x00]
- swi $r2, [$r0+#0x04]
- move $lp, $r11
- ret
-
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
-.globl lowlevel_init
-lowlevel_init:
- move $r10, $lp
- jal remap
-
-#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
- jal enable_fpu
-#endif
- ret $r10
-
-remap:
- move $r11, $lp
-relo_base:
- mfusr $r0, $pc
-
-#ifdef CONFIG_MEM_REMAP
- li $r4, 0x00000000
- li $r5, 0x80000000
- la $r6, _end@GOTOFF
-1:
- lmw.bim $r12, [$r5], $r19
- smw.bim $r12, [$r4], $r19
- blt $r5, $r6, 1b
-#endif /* #ifdef CONFIG_MEM_REMAP */
- move $lp, $r11
-2:
- ret
-
- /*
- * enable_fpu:
- * Some of Andes CPU version support FPU coprocessor, if so,
- * and toolchain support FPU instruction set, we should enable it.
- */
-#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
-enable_fpu:
- mfsr $r0, $CPU_VER /* enable FPU if it exists */
- srli $r0, $r0, 3
- andi $r0, $r0, 1
- beqz $r0, 1f /* skip if no COP */
- mfsr $r0, $FUCOP_EXIST
- srli $r0, $r0, 31
- beqz $r0, 1f /* skip if no FPU */
- mfsr $r0, $FUCOP_CTL
- ori $r0, $r0, 1
- mtsr $r0, $FUCOP_CTL
-1:
- ret
-#endif
-
-#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-#ifndef CONFIG_TIMER
-#include <common.h>
-#include <asm/io.h>
-#include <faraday/fttmr010.h>
-#error "AE3XX timer only support DM flow"
-#endif /* CONFIG_TIMER */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#include <asm/arch-ag101/ag101.h>
-#include <linux/linkage.h>
-
-.text
-
-#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
-ENTRY(turnoff_watchdog)
-#error "AE3XX not support wdt yet"
-ENDPROC(turnoff_watchdog)
-#endif
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2009
-# Marvell Semiconductor <www.marvell.com>
-# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
-#
-# Copyright (C) 2011 Andes Technology Corporation
-# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
-# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
-
-obj-y := cpu.o timer.o
-obj-y += lowlevel_init.o
-
-ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
-obj-y += watchdog.o
-endif
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-/* CPU specific code */
-#include <common.h>
-#include <command.h>
-#include <cpu_func.h>
-#include <irq_func.h>
-#include <watchdog.h>
-#include <asm/cache.h>
-
-#include <faraday/ftwdt010_wdt.h>
-
-/*
- * cleanup_before_linux() is called just before we call linux
- * it prepares the processor for linux
- *
- * we disable interrupt and caches.
- */
-int cleanup_before_linux(void)
-{
- disable_interrupts();
-
- /* turn off I/D-cache */
- cache_flush();
- icache_disable();
- dcache_disable();
- return 0;
-}
-
-int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
-{
- disable_interrupts();
-
- /*
- * reset to the base addr of andesboot.
- * currently no ROM loader at addr 0.
- * do not use reset_cpu();
- */
-#ifdef CONFIG_FTWDT010_WATCHDOG
- /*
- * workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
- * automatic hardware reset when booting Linux.
- * Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
- */
- ftwdt010_wdt_reset();
- while (1)
- ;
-#endif /* CONFIG_FTWDT010_WATCHDOG */
-
- /*NOTREACHED*/
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-.pic
-
-.text
-
-#include <common.h>
-#include <config.h>
-
-#include <asm/macro.h>
-#include <generated/asm-offsets.h>
-
-/*
- * parameters for the SDRAM controller
- */
-#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
-#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
-#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
-#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
-#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
-#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
-
-#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
-#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
-#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
-#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
-
-#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
-#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
-
-
-/*
- * for Orca and Emerald
- */
-#define BOARD_ID_REG 0x104
-#define BOARD_ID_FAMILY_MASK 0xfff000
-#define BOARD_ID_FAMILY_V5 0x556000
-#define BOARD_ID_FAMILY_K7 0x74b000
-
-/*
- * parameters for the static memory controller
- */
-#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
-#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
-
-#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
-#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
-
-/*
- * parameters for the ahbc controller
- */
-#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
-#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
-
-/*
- * for Orca and Emerald
- */
-#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
-#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
-
-/*
- * parameters for the pmu controoler
- */
-#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
-
-/*
- * numeric 7 segment display
- */
-.macro led, num
- write32 CONFIG_DEBUG_LED, \num
-.endm
-
-/*
- * Waiting for SDRAM to set up
- */
-.macro wait_sdram
- li $r0, CONFIG_FTSDMC021_BASE
-1:
- lwi $r1, [$r0+FTSDMC021_CR2]
- bnez $r1, 1b
-.endm
-
-.globl mem_init
-mem_init:
- move $r11, $lp
-
- /*
- * mem_init:
- * There are 2 bank connected to FTSMC020 on AG101
- * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
- * we need to set onboard SDRAM before remap and relocation.
- */
- led 0x01
-
- /*
- * for Orca and Emerald
- * disable write protection and reset bank size
- */
- li $r0, SMC_BANK0_CR_A
- lwi $r1, [$r0+#0x00]
- ori $r1, $r1, 0x8f0
- xori $r1, $r1, 0x8f0
- /* check board */
- li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
- lwi $r3, [$r3]
- li $r4, BOARD_ID_FAMILY_MASK
- and $r3, $r3, $r4
- li $r4, BOARD_ID_FAMILY_K7
- xor $r4, $r3, $r4
- beqz $r4, use_flash_16bit_boot
- /* 32-bit mode */
-use_flash_32bit_boot:
- ori $r1, $r1, 0x50
- li $r2, 0x00151151
- j sdram_b0_cr
- /* 16-bit mode */
-use_flash_16bit_boot:
- ori $r1, $r1, 0x60
- li $r2, 0x00153153
- /* SRAM bank0 config */
-sdram_b0_cr:
- swi $r1, [$r0+#0x00]
- swi $r2, [$r0+#0x04]
-
- /* config AHB Controller */
- led 0x02
-
- /*
- * config PMU controller
- */
- /* ftpmu010_dlldis_disable, must do it in lowleve_init */
- led 0x03
- setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
-
- /*
- * config SDRAM controller
- */
- led 0x04
- write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
- led 0x05
- write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
- led 0x06
- write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
-
- led 0x07
- write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
- wait_sdram
-
- led 0x08
- write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
- wait_sdram
-
- led 0x09
- write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
- wait_sdram
-
- led 0x0a
- move $lp, $r11
- ret
-
-
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
-
-.globl lowlevel_init
-lowlevel_init:
- move $r10, $lp
- led 0x10
- jal remap
-#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
- led 0x1f
- jal enable_fpu
-#endif
- led 0x20
- ret $r10
-
-remap:
- move $r11, $lp
-#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
- bal 2f
-relo_base:
- move $r0, $lp
-#else
-relo_base:
- mfusr $r0, $pc
-#endif /* __NDS32_N1213_43U1H__ */
-
- /* Remapping */
- led 0x1a
- write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
- write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
-
- /* clear empty BSR registers */
- led 0x1b
- li $r4, CONFIG_FTSDMC021_BASE
- li $r5, 0x0
- swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
- swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
-
-#ifdef CONFIG_MEM_REMAP
- /*
- * Copy ROM code to SDRAM base for memory remap layout.
- * This is not the real relocation, the real relocation is the function
- * relocate_code() is start.S which supports the systems is memory
- * remapped or not.
- */
- /*
- * Doing memory remap is essential for preparing some non-OS or RTOS
- * applications.
- *
- * This is also a must on ADP-AG101 board.
- * The reason is because the ROM/FLASH circuit on PCB board.
- * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
- * ROM/FLASH is used to boot.
- *
- * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
- * and the FLASH is connected to BANK1.
- * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
- * and the FLASH is connected to BANK0.
- * It will occur problem when doing flash probing if the flash is at
- * BANK0 (0x00000000) while memory remapping was skipped.
- *
- * Other board like ADP-AG101P may not enable this since there is only
- * a FLASH connected to bank0.
- */
- led 0x11
- /*
- * for Orca and Emerald
- * read sdram base address automatically
- */
- li $r5, AHBC_BSR6_A
- lwi $r8, [$r5]
- li $r4, 0xfff00000 /* r4 = bank6 base */
- and $r4, $r4, $r8
-
- la $r5, _start@GOTOFF
- la $r6, _end@GOTOFF
-1:
- lwi.p $r7, [$r5], #4
- swi.p $r7, [$r4], #4
- blt $r5, $r6, 1b
-
- /* set remap bit */
- /*
- * MEM remap bit is operational
- * - use it to map writeable memory at 0x00000000, in place of flash
- * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
- * - after remap: flash/rom 0x80000000, sdram: 0x00000000
- */
- led 0x1c
- write32 SDMC_B0_BSR_A, 0x00001000
- write32 SDMC_B1_BSR_A, 0x00001200
- li $r5, CONFIG_SYS_TEXT_BASE /* flash base address */
- add $r11, $r11, $r5 /* add flash address offset for ret */
- add $r10, $r10, $r5
- move $lp, $r11
- setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
-
- /*
- * for Orca and Emerald
- * extend sdram size from 256MB to 2GB
- */
- li $r5, AHBC_BSR6_A
- lwi $r6, [$r5]
- li $r4, 0xfff0ffff
- and $r6 ,$r4, $r6
- li $r4, 0x000b0000
- or $r6, $r4, $r6
- swi $r6, [$r5]
-
- /*
- * for Orca and Emerald
- * extend rom base from 256MB to 2GB
- */
- li $r4, AHBC_BSR4_A
- lwi $r5, [$r4]
- li $r6, 0xffffff
- and $r5, $r5, $r6
- li $r6, 0x80000000
- or $r5, $r5, $r6
- swi $r5, [$r4]
-#endif /* #ifdef CONFIG_MEM_REMAP */
- move $lp, $r11
-2:
- ret
-
- /*
- * enable_fpu:
- * Some of Andes CPU version support FPU coprocessor, if so,
- * and toolchain support FPU instruction set, we should enable it.
- */
-#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
-enable_fpu:
- mfsr $r0, $CPU_VER /* enable FPU if it exists */
- srli $r0, $r0, 3
- andi $r0, $r0, 1
- beqz $r0, 1f /* skip if no COP */
- mfsr $r0, $FUCOP_EXIST
- srli $r0, $r0, 31
- beqz $r0, 1f /* skip if no FPU */
- mfsr $r0, $FUCOP_CTL
- ori $r0, $r0, 1
- mtsr $r0, $FUCOP_CTL
-1:
- ret
-#endif
-
-.globl show_led
-show_led:
- li $r8, (CONFIG_DEBUG_LED)
- swi $r7, [$r8]
- ret
-#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <ratbert@faraday-tech.com>
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-#ifndef CONFIG_TIMER
-#include <common.h>
-#include <clock_legacy.h>
-#include <init.h>
-#include <irq_func.h>
-#include <log.h>
-#include <time.h>
-#include <asm/io.h>
-#include <faraday/fttmr010.h>
-#include <linux/delay.h>
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
- unsigned int cr;
-
- debug("%s()\n", __func__);
-
- /* disable timers */
- writel(0, &tmr->cr);
-
-#ifdef CONFIG_FTTMR010_EXT_CLK
- /* use 32768Hz oscillator for RTC, WDT, TIMER */
- ftpmu010_32768osc_enable();
-#endif
-
- /* setup timer */
- writel(TIMER_LOAD_VAL, &tmr->timer3_load);
- writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
- writel(0, &tmr->timer3_match1);
- writel(0, &tmr->timer3_match2);
-
- /* we don't want timer to issue interrupts */
- writel(FTTMR010_TM3_MATCH1 |
- FTTMR010_TM3_MATCH2 |
- FTTMR010_TM3_OVERFLOW,
- &tmr->interrupt_mask);
-
- cr = readl(&tmr->cr);
-#ifdef CONFIG_FTTMR010_EXT_CLK
- cr |= FTTMR010_TM3_CLOCK; /* use external clock */
-#endif
- cr |= FTTMR010_TM3_ENABLE;
- writel(cr, &tmr->cr);
-
- /* init the timestamp and lastdec value */
- reset_timer_masked();
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-/*
- * reset time
- */
-void reset_timer_masked(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-
- /* capure current decrementer value time */
-#ifdef CONFIG_FTTMR010_EXT_CLK
- lastdec = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-#else
- lastdec = readl(&tmr->timer3_counter) /
- (get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
-#endif
- timestamp = 0; /* start "advancing" time stamp from 0 */
-
- debug("%s(): lastdec = %lx\n", __func__, lastdec);
-}
-
-void reset_timer(void)
-{
- debug("%s()\n", __func__);
- reset_timer_masked();
-}
-
-/*
- * return timer ticks
- */
-ulong get_timer_masked(void)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-
- /* current tick value */
-#ifdef CONFIG_FTTMR010_EXT_CLK
- ulong now = readl(&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-#else
- ulong now = readl(&tmr->timer3_counter) /
- (get_board_sys_clk() / 2 / CONFIG_SYS_HZ);
-#endif
-
- debug("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec);
-
- if (lastdec >= now) {
- /*
- * normal mode (non roll)
- * move stamp fordward with absoulte diff ticks
- */
- timestamp += lastdec - now;
- } else {
- /*
- * we have overflow of the count down timer
- *
- * nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll and
- * cause problems.
- */
- timestamp += lastdec + TIMER_LOAD_VAL - now;
- }
-
- lastdec = now;
-
- debug("%s() returns %lx\n", __func__, timestamp);
-
- return timestamp;
-}
-
-/*
- * return difference between timer ticks and base
- */
-ulong get_timer(ulong base)
-{
- debug("%s(%lx)\n", __func__, base);
- return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
- debug("%s(%lx)\n", __func__, t);
- timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay(unsigned long usec)
-{
- struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
-
-#ifdef CONFIG_FTTMR010_EXT_CLK
- long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-#else
- long tmo = usec * ((get_board_sys_clk() / 2) / 1000) / 1000;
-#endif
- unsigned long now, last = readl(&tmr->timer3_counter);
-
- debug("%s(%lu)\n", __func__, usec);
- while (tmo > 0) {
- now = readl(&tmr->timer3_counter);
- if (now > last) /* count down timer overflow */
- tmo -= TIMER_LOAD_VAL + last - now;
- else
- tmo -= last - now;
- last = now;
- }
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- debug("%s()\n", __func__);
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- debug("%s()\n", __func__);
-#ifdef CONFIG_FTTMR010_EXT_CLK
- return CONFIG_SYS_HZ;
-#else
- return get_board_sys_clk();
-#endif
-}
-#endif /* CONFIG_TIMER */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#include <asm/arch-ag101/ag101.h>
-#include <linux/linkage.h>
-
-.text
-
-#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
-ENTRY(turnoff_watchdog)
-
-#define WD_CR 0xC
-#define WD_ENABLE 0x1
-
- ! Turn off the watchdog, according to Faraday FTWDT010 spec
- li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
- lwi $p1, [$p0] ! Get the config of WD
- andi $p1, $p1, 0x1f ! Wipe out useless bits
- li $r0, ~WD_ENABLE
- and $p1, $p1, $r0 ! Set WD disable
- sw $p1, [$p0] ! Write back to WD CR
-
- ! Disable Interrupts by clear GIE in $PSW reg
- setgie.d
-
- ret
-
-ENDPROC(turnoff_watchdog)
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Andesboot - Startup Code for Whitiger core
- *
- * Copyright (C) 2006 Andes Technology Corporation
- * Copyright (C) 2006 Shawn Lin <nobuhiro@andestech.com>
- * Copyright (C) 2011 Macpaul Lin <macpaul@andestech.com>
- * Greentime Hu <greentime@andestech.com>
- */
-
-.pic
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <common.h>
-#include <asm/macro.h>
-
-/*
- * Jump vector table for EVIC mode
- */
-#define ENA_DCAC 2UL
-#define DIS_DCAC ~ENA_DCAC
-#define ICAC_MEM_KBF_ISET (0x07) ! I Cache sets per way
-#define ICAC_MEM_KBF_IWAY (0x07<<3) ! I cache ways
-#define ICAC_MEM_KBF_ISZ (0x07<<6) ! I cache line size
-#define DCAC_MEM_KBF_DSET (0x07) ! D Cache sets per way
-#define DCAC_MEM_KBF_DWAY (0x07<<3) ! D cache ways
-#define DCAC_MEM_KBF_DSZ (0x07<<6) ! D cache line size
-
-#define PSW $ir0
-#define EIT_INTR_PSW $ir1 ! interruption $PSW
-#define EIT_PREV_IPSW $ir2 ! previous $IPSW
-#define EIT_IVB $ir3 ! intr vector base address
-#define EIT_EVA $ir4 ! MMU related Exception VA reg
-#define EIT_PREV_EVA $ir5 ! previous $eva
-#define EIT_ITYPE $ir6 ! interruption type
-#define EIT_PREV_ITYPE $ir7 ! prev intr type
-#define EIT_MACH_ERR $ir8 ! machine error log
-#define EIT_INTR_PC $ir9 ! Interruption PC
-#define EIT_PREV_IPC $ir10 ! previous $IPC
-#define EIT_OVL_INTR_PC $ir11 ! overflow interruption PC
-#define EIT_PREV_P0 $ir12 ! prev $P0
-#define EIT_PREV_P1 $ir13 ! prev $p1
-#define CR_ICAC_MEM $cr1 ! I-cache/memory config reg
-#define CR_DCAC_MEM $cr2 ! D-cache/memory config reg
-#define MR_CAC_CTL $mr8
-
-.globl _start
-
-_start: j reset
- j tlb_fill
- j tlb_not_present
- j tlb_misc
- j tlb_vlpt_miss
- j machine_error
- j debug
- j general_exception
- j syscall
- j internal_interrupt ! H0I
- j internal_interrupt ! H1I
- j internal_interrupt ! H2I
- j internal_interrupt ! H3I
- j internal_interrupt ! H4I
- j internal_interrupt ! H5I
- j software_interrupt ! S0I
-
- .balign 16
-
-/*
- * Andesboot Startup Code (reset vector)
- *
- * 1. bootstrap
- * 1.1 reset - start of u-boot
- * 1.2 to superuser mode - as is when reset
- * 1.4 Do lowlevel_init
- * - (this will jump out to lowlevel_init.S in SoC)
- * - (lowlevel_init)
- * 1.3 Turn off watchdog timer
- * - (this will jump out to watchdog.S in SoC)
- * - (turnoff_watchdog)
- * 2. Do critical init when reboot (not from mem)
- * 3. Relocate andesboot to ram
- * 4. Setup stack
- * 5. Jump to second stage (board_init_r)
- */
-
-/* Note: TEXT_BASE is defined by the (board-dependent) linker script */
-.globl _TEXT_BASE
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * The bootstrap code of nds32 core
- */
-
-reset:
-
-/*
- * gp = ~0 for burn mode
- * = ~load_address for load mode
- */
-reset_gp:
- .relax_hint 0
- sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
- .relax_hint 0
- ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
- add5.pc $gp
-
-set_ivb:
- li $r0, 0x0
- /* turn on BTB */
- mtsr $r0, $misc_ctl
- /* set IVIC, vector size: 4 bytes, base: 0x0 */
- mtsr $r0, $ivb
-/*
- * MMU_CTL NTC0 Non-cacheable
- */
- li $r0, ~0x6
- mfsr $r1, $mr0
- and $r1, $r1, $r0
- mtsr $r1, $mr0
-
- li $r0, ~0x3
- mfsr $r1, $mr8
- and $r1, $r1, $r0
- mtsr $r1, $mr8
-#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
-/*
- * MMU_CTL NTC0 Cacheable/Write-Back
- */
- li $r0, 0x4
- mfsr $r1, $mr0
- or $r1, $r1, $r0
- mtsr $r1, $mr0
-#endif
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_ARCH_MAP_SYSMEM
-/*
- * MMU_CTL NTC1 Non-cacheable
- */
- li $r0, ~0x18
- mfsr $r1, $mr0
- and $r1, $r1, $r0
- mtsr $r1, $mr0
-/*
- * MMU_CTL NTM1 mapping for partition 0
- */
- li $r0, ~0x6000
- mfsr $r1, $mr0
- and $r1, $r1, $r0
- mtsr $r1, $mr0
-#endif
-#endif
-
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
- li $r0, 0x1
- mfsr $r1, $mr8
- or $r1, $r1, $r0
- mtsr $r1, $mr8
-#endif
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
- li $r0, 0x2
- mfsr $r1, $mr8
- or $r1, $r1, $r0
- mtsr $r1, $mr8
-#endif
-
- jal mem_init
-
-#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
- jal lowlevel_init
-/*
- * gp = ~VMA for burn mode
- * = ~load_address for load mode
- */
-update_gp:
- .relax_hint 0
- sethi $gp, hi20(_GLOBAL_OFFSET_TABLE_-8)
- .relax_hint 0
- ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4)
- add5.pc $gp
-#endif
-/*
- * do critical initializations first (shall be in short time)
- * do self_relocation ASAP.
- */
-
-/*
- * Set the N1213 (Whitiger) core to superuser mode
- * According to spec, it is already when reset
- */
-#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
- jal turnoff_watchdog
-#endif
-
-/*
- * Set stackpointer in internal RAM to call board_init_f
- * $sp must be 8-byte alignment for ABI compliance.
- */
-call_board_init_f:
- li $sp, CONFIG_SYS_INIT_SP_ADDR
- move $r0, $sp
- bal board_init_f_alloc_reserve
- move $sp, $r0
- bal board_init_f_init_reserve
-#ifdef CONFIG_DEBUG_UART
- bal debug_uart_init
-#endif
- li $r0, 0x00000000
-#ifdef __PIC__
-#ifdef __NDS32_N1213_43U1H__
-/* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */
- la $r15, board_init_f ! store function address into $r15
-#endif
-#endif
- j board_init_f ! jump to board_init_f() in lib/board.c
-
-/*
- * void relocate_code(addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-
-/*
- * gp = ~RAM_SIZE - TEXT_SIZE for burn/load mode
- */
-
-.globl relocate_code
-relocate_code:
- move $r4, $r0 /* save addr_sp */
- move $r5, $r1 /* save addr of gd */
- move $r6, $r2 /* save addr of destination */
-
-/* Set up the stack */
-stack_setup:
- move $sp, $r4
-
- la $r0, _start@GOTOFF
- beq $r0, $r6, clear_bss /* skip relocation */
-
- la $r1, _end@GOTOFF
- move $r2, $r6 /* r2 <- scratch for copy_loop */
-copy_loop:
- lmw.bim $r11, [$r0], $r18
- smw.bim $r11, [$r2], $r18
- blt $r0, $r1, copy_loop
-/*
- * fix relocations related issues
- */
-fix_relocations:
- l.w $r0, _TEXT_BASE@GOTOFF /* r0 <- Text base */
- sub $r9, $r6, $r0 /* r9 <- relocation offset */
-
- la $r7, __rel_dyn_start@GOTOFF
- add $r7, $r7, $r9 /* r2 <- rel __got_start in RAM */
- la $r8, __rel_dyn_end@GOTOFF
- add $r8, $r8, $r9 /* r2 <- rel __got_start in RAM */
- li $r3, #0x2a /* R_NDS32_RELATIVE */
-1:
- lmw.bim $r0, [$r7], $r2 /* r0,r1,r2 <- adr,type,addend */
- bne $r1, $r3, 2f
-
- add $r0, $r0, $r9
- add $r2, $r2, $r9
- sw $r2, [$r0]
-2:
- blt $r7, $r8, 1b
-
-clear_bss:
- la $r0, __bss_start@GOTOFF /* r0 <- rel __bss_start in FLASH */
- add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */
- la $r1, __bss_end@GOTOFF /* r1 <- rel __bss_end in RAM */
- add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */
- li $r2, 0x00000000 /* clear */
-
-clbss_l:
- sw $r2, [$r0] /* clear loop... */
- addi $r0, $r0, #4
- bne $r0, $r1, clbss_l
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-call_board_init_r:
- bal invalidate_icache_all
- bal flush_dcache_all
- la $r0, board_init_r@GOTOFF
- move $lp, $r0 /* offset of board_init_r() */
- add $lp, $lp, $r9 /* real address of board_init_r() */
- /* setup parameters for board_init_r */
- move $r0, $r5 /* gd_t */
- move $r1, $r6 /* dest_addr */
-
-#ifdef __PIC__
-#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA */
- move $r15, $lp /* store function address into $r15 */
-#endif
-#endif
-
- /* jump to it ... */
- jr $lp /* jump to board_init_r() */
-
-/*
- * Invalidate I$
- */
-invalidate_icac:
- ! read $cr1(I CAC/MEM cfg. reg.) configuration
- mfsr $t0, CR_ICAC_MEM
-
- ! Get the ISZ field
- andi $p0, $t0, ICAC_MEM_KBF_ISZ
-
- ! if $p0=0, then no I CAC existed
- beqz $p0, end_flush_icache
-
- ! get $p0 the index of I$ block
- srli $p0, $p0, 6
-
- ! $t1= bit width of I cache line size(ISZ)
- addi $t1, $p0, 2
-
- li $t4, 1
- sll $t5, $t4, $t1 ! get $t5 cache line size
- andi $p1, $t0, ICAC_MEM_KBF_ISET ! get the ISET field
- addi $t2, $p1, 6 ! $t2= bit width of ISET
- andi $p1, $t0, ICAC_MEM_KBF_IWAY ! get bitfield of Iway
- srli $p1, $p1, 3
- addi $p1, $p1, 1 ! then $p1 is I way number
- add $t3, $t2, $t1 ! SHIFT
- sll $p1, $p1, $t3 ! GET the total cache size
-ICAC_LOOP:
- sub $p1, $p1, $t5
- cctl $p1, L1I_IX_INVAL
- bnez $p1, ICAC_LOOP
-end_flush_icache:
- ret
-
-/*
- * Invalidate D$
- */
-invalidate_dcac:
- ! read $cr2(D CAC/MEM cfg. reg.) configuration
- mfsr $t0, CR_DCAC_MEM
-
- ! Get the DSZ field
- andi $p0, $t0, DCAC_MEM_KBF_DSZ
-
- ! if $p0=0, then no D CAC existed
- beqz $p0, end_flush_dcache
-
- ! get $p0 the index of D$ block
- srli $p0, $p0, 6
-
- ! $t1= bit width of D cache line size(DSZ)
- addi $t1, $p0, 2
-
- li $t4, 1
- sll $t5, $t4, $t1 ! get $t5 cache line size
- andi $p1, $t0, DCAC_MEM_KBF_DSET ! get the DSET field
- addi $t2, $p1, 6 ! $t2= bit width of DSET
- andi $p1, $t0, DCAC_MEM_KBF_DWAY ! get bitfield of D way
- srli $p1, $p1, 3
- addi $p1, $p1, 1 ! then $p1 is D way number
- add $t3, $t2, $t1 ! SHIFT
- sll $p1, $p1, $t3 ! GET the total cache size
-DCAC_LOOP:
- sub $p1, $p1, $t5
- cctl $p1, L1D_IX_INVAL
- bnez $p1, DCAC_LOOP
-end_flush_dcache:
- ret
-
-/*
- * Interrupt handling
- */
-
-/*
- * exception handlers
- */
- .align 5
-
-.macro SAVE_ALL
- ! FIXME: Other way to get PC?
- ! FIXME: Update according to the newest spec!!
-1:
- li $r28, 1
- push $r28
- mfsr $r28, PSW ! $PSW
- push $r28
- mfsr $r28, EIT_EVA ! $ir1 $EVA
- push $r28
- mfsr $r28, EIT_ITYPE ! $ir2 $ITYPE
- push $r28
- mfsr $r28, EIT_MACH_ERR ! $ir3 Mach Error
- push $r28
- mfsr $r28, EIT_INTR_PSW ! $ir5 $IPSW
- push $r28
- mfsr $r28, EIT_PREV_IPSW ! $ir6 prev $IPSW
- push $r28
- mfsr $r28, EIT_PREV_EVA ! $ir7 prev $EVA
- push $r28
- mfsr $r28, EIT_PREV_ITYPE ! $ir8 prev $ITYPE
- push $r28
- mfsr $r28, EIT_INTR_PC ! $ir9 Interruption PC
- push $r28
- mfsr $r28, EIT_PREV_IPC ! $ir10 prev INTR_PC
- push $r28
- mfsr $r28, EIT_OVL_INTR_PC ! $ir11 Overflowed INTR_PC
- push $r28
- mfusr $r28, $d1.lo
- push $r28
- mfusr $r28, $d1.hi
- push $r28
- mfusr $r28, $d0.lo
- push $r28
- mfusr $r28, $d0.hi
- push $r28
- pushm $r0, $r30 ! store $sp-$r31, ra-$r30, $gp-$r29, $r28-$fp
- addi $sp, $sp, -4 ! make room for implicit pt_regs parameters
-.endm
-
- .align 5
-tlb_fill:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 1 ! Determine interruption type
- bal do_interruption
-
- .align 5
-tlb_not_present:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 2 ! Determine interruption type
- bal do_interruption
-
- .align 5
-tlb_misc:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 3 ! Determine interruption type
- bal do_interruption
-
- .align 5
-tlb_vlpt_miss:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 4 ! Determine interruption type
- bal do_interruption
-
- .align 5
-machine_error:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 5 ! Determine interruption type
- bal do_interruption
-
- .align 5
-debug:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 6 ! Determine interruption type
- bal do_interruption
-
- .align 5
-general_exception:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 7 ! Determine interruption type
- bal do_interruption
-
- .align 5
-syscall:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 8 ! Determine interruption type
- bal do_interruption
-
- .align 5
-internal_interrupt:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 9 ! Determine interruption type
- bal do_interruption
-
- .align 5
-software_interrupt:
- SAVE_ALL
- move $r0, $sp ! To get the kernel stack
- li $r1, 10 ! Determine interruption type
- bal do_interruption
-
- .align 5
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
-OUTPUT_ARCH(nds32)
-ENTRY(_start)
-SECTIONS
-{
- . = ALIGN(4);
- .text :
- {
- arch/nds32/cpu/n1213/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : { *(.data*) }
-
- . = ALIGN(4);
-
- .got : {
- __got_start = .;
- *(.got.plt) *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
- . = ALIGN(4);
- /DISCARD/ : { *(.rela.plt*) }
- .rela.dyn : {
- __rel_dyn_start = .;
- *(.rela*)
- __rel_dyn_end = .;
- }
- _end = .;
-
- .bss : {
- __bss_start = .;
- *(.bss)
- . = ALIGN(4);
- __bss_end = .;
- }
-
-}
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-
-dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb
-dtb-$(CONFIG_TARGET_ADP_AE3XX) += ae3xx.dtb
-include $(srctree)/scripts/Makefile.dts
-
-targets += $(dtb-y)
-
-DTC_FLAGS += -R 4 -p 0x1000
-
-PHONY += dtbs
-dtbs: $(addprefix $(obj)/, $(dtb-y))
- @:
-
-clean-files := *.dtb
+++ /dev/null
-/dts-v1/;
-/ {
- compatible = "nds32 ae3xx";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- aliases {
- uart0 = &serial0;
- ethernet0 = &mac0;
- spi0 = &spi;
- } ;
-
- chosen {
- /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */
- bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
- stdout-path = "uart0:38400n8";
- tick-timer = &timer0;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x40000000>;
- };
-
- spiclk: virt_100mhz {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- compatible = "andestech,n13";
- reg = <0>;
- /* FIXME: to fill correct frqeuency */
- clock-frequency = <60000000>;
- };
- };
-
- intc: interrupt-controller {
- compatible = "andestech,atnointc010";
- #interrupt-cells = <1>;
- interrupt-controller;
- };
-
- serial0: serial@f0300000 {
- compatible = "andestech,uart16550", "ns16550a";
- reg = <0xf0300000 0x1000>;
- interrupts = <7 4>;
- clock-frequency = <14745600>;
- reg-shift = <2>;
- reg-offset = <32>;
- no-loopback-test = <1>;
- };
-
- timer0: timer@f0400000 {
- compatible = "andestech,atcpit100";
- reg = <0xf0400000 0x1000>;
- interrupts = <2 4>;
- clock-frequency = <30000000>;
- };
-
- mac0: mac@e0100000 {
- compatible = "andestech,atmac100";
- reg = <0xe0100000 0x1000>;
- interrupts = <25 4>;
- };
-
- mmc0: mmc@f0e00000 {
- compatible = "andestech,atfsdc010";
- max-frequency = <100000000>;
- fifo-depth = <0x10>;
- reg = <0xf0e00000 0x1000>;
- interrupts = <17 4>;
- };
-
- nor@0,0 {
- compatible = "cfi-flash";
- reg = <0x88000000 0x1000>;
- bank-width = <2>;
- device-width = <1>;
- };
-
- spi: spi@f0b00000 {
- compatible = "andestech,atcspi200";
- reg = <0xf0b00000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- num-cs = <1>;
- clocks = <&spiclk>;
- interrupts = <3 4>;
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- spi-cpol;
- spi-cpha;
- };
- };
-};
+++ /dev/null
-/dts-v1/;
-/ {
- compatible = "nds32 ag101p";
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
-
- aliases {
- uart0 = &serial0;
- ethernet0 = &mac0;
- } ;
-
- chosen {
- /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
- bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
- stdout-path = "uart0:38400n8";
- tick-timer = &timer0;
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x40000000>;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- compatible = "andestech,n13";
- reg = <0>;
- /* FIXME: to fill correct frqeuency */
- clock-frequency = <60000000>;
- };
- };
-
- intc: interrupt-controller {
- compatible = "andestech,atnointc010";
- #interrupt-cells = <1>;
- interrupt-controller;
- };
-
- serial0: serial@99600000 {
- compatible = "andestech,uart16550", "ns16550a";
- reg = <0x99600000 0x1000>;
- interrupts = <7 4>;
- clock-frequency = <14745600>;
- reg-shift = <2>;
- no-loopback-test = <1>;
- };
-
- timer0: timer@98400000 {
- compatible = "andestech,attmr010";
- reg = <0x98400000 0x1000>;
- interrupts = <19 4>;
- clock-frequency = <15000000>;
- };
-
- mac0: mac@90900000 {
- compatible = "andestech,atmac100";
- reg = <0x90900000 0x1000>;
- interrupts = <25 4>;
- };
-
- mmc0: mmc@98e00000 {
- compatible = "andestech,atfsdc010";
- max-frequency = <30000000>;
- fifo-depth = <0x10>;
- reg = <0x98e00000 0x1000>;
- interrupts = <5 4>;
- cap-sd-highspeed;
- };
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2016 Andes Technology Corporation
- * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __AE3XX_H
-#define __AE3XX_H
-
-/* Hardware register bases */
-
-/* Static Memory Controller (SRAM) */
-#define CONFIG_FTSMC020_BASE 0xe0400000
-/* DMA Controller */
-#define CONFIG_FTDMAC020_BASE 0xf0c00000
-/* AHB-to-APB Bridge */
-#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000
-/* Reserved */
-#define CONFIG_RESERVED_01_BASE 0xe0500000
-/* Reserved */
-#define CONFIG_RESERVED_02_BASE 0xf0800000
-/* Reserved */
-#define CONFIG_RESERVED_03_BASE 0xf0900000
-/* Ethernet */
-#define CONFIG_FTMAC100_BASE 0xe0100000
-/* Reserved */
-#define CONFIG_RESERVED_04_BASE 0xf1000000
-
-/* APB Device definitions */
-
-/* UART1 */
-#define CONFIG_FTUART010_01_BASE 0xf0200000
-/* UART2 */
-#define CONFIG_FTUART010_02_BASE 0xf0300000
-/* Counter/Timers */
-#define CONFIG_FTTMR010_BASE 0xf0400000
-/* Watchdog Timer */
-#define CONFIG_FTWDT010_BASE 0xf0500000
-/* Real Time Clock */
-#define CONFIG_FTRTC010_BASE 0xf0600000
-/* GPIO */
-#define CONFIG_FTGPIO010_BASE 0xf0700000
-/* I2C */
-#define CONFIG_FTIIC010_BASE 0xf0a00000
-
-/* The following address was not defined in Linux */
-
-/* Synchronous Serial Port Controller (SSP) 01 */
-#define CONFIG_FTSSP010_01_BASE 0xf0d00000
-#endif /* __AE3XX_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __AG101_H
-#define __AG101_H
-
-/* Hardware register bases */
-
-/* AHB Controller */
-#define CONFIG_FTAHBC020S_BASE 0x90100000
-/* Static Memory Controller (SRAM) */
-#define CONFIG_FTSMC020_BASE 0x90200000
-/* FTSDMC021 SDRAM Controller */
-#define CONFIG_FTSDMC021_BASE 0x90300000
-/* DMA Controller */
-#define CONFIG_FTDMAC020_BASE 0x90400000
-/* AHB-to-APB Bridge */
-#define CONFIG_FTAPBBRG020S_01_BASE 0x90500000
-/* LCD Controller */
-#define CONFIG_FTLCDC100_BASE 0x90600000
-/* Reserved */
-#define CONFIG_RESERVED_01_BASE 0x90700000
-/* Reserved */
-#define CONFIG_RESERVED_02_BASE 0x90800000
-/* Ethernet */
-#define CONFIG_FTMAC100_BASE 0x90900000
-/* External USB host */
-#define CONFIG_EXT_USB_HOST_BASE 0x90A00000
-/* USB Device */
-#define CONFIG_USB_DEV_BASE 0x90B00000
-/* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */
-#define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000
-/* Reserved */
-#define CONFIG_RESERVED_03_BASE 0x90D00000
-/* External AHB-to-APB Bridger (FTAPBBRG020S_02) */
-#define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000
-/* External AHB slave1 (LCD) */
-#define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000
-/* External AHB slave2 (FUSBH200) */
-#define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000
-
-/* APB Device definitions */
-
-/* Power Management Unit */
-#define CONFIG_FTPMU010_BASE 0x98100000
-/* BT UART 2/IrDA (UART 01 in Linux) */
-#define CONFIG_FTUART010_01_BASE 0x98300000
-/* Counter/Timers */
-#define CONFIG_FTTMR010_BASE 0x98400000
-/* Watchdog Timer */
-#define CONFIG_FTWDT010_BASE 0x98500000
-/* Real Time Clock */
-#define CONFIG_FTRTC010_BASE 0x98600000
-/* GPIO */
-#define CONFIG_FTGPIO010_BASE 0x98700000
-/* Interrupt Controller */
-#define CONFIG_FTINTC010_BASE 0x98800000
-/* I2C */
-#define CONFIG_FTIIC010_BASE 0x98A00000
-/* Reserved */
-#define CONFIG_RESERVED_04_BASE 0x98C00000
-/* Compat Flash Controller */
-#define CONFIG_FTCFC010_BASE 0x98D00000
-
-/* Synchronous Serial Port Controller (SSP) I2S/AC97 */
-#define CONFIG_FTSSP010_02_BASE 0x99400000
-/* ST UART ? SSP 02 (UART 02 in Linux) */
-#define CONFIG_FTUART010_02_BASE 0x99600000
-
-/* The following address was not defined in Linux */
-
-/* FF UART 3 */
-#define CONFIG_FTUART010_03_BASE 0x98200000
-/* Synchronous Serial Port Controller (SSP) 01 */
-#define CONFIG_FTSSP010_01_BASE 0x98B00000
-/* IrDA */
-#define CONFIG_IRDA_BASE 0x98900000
-/* PWM - Pulse Width Modulator Controller */
-#define CONFIG_PMW_BASE 0x99100000
-
-#endif /* __AG101_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __AG102_H
-#define __AG102_H
-
-/*
- * Hardware register bases
- */
-
-/* LPC Controller */
-#define CONFIG_LPC_IO_BASE 0x90100000
-/* LPC Controller */
-#define CONFIG_LPC_BASE 0x90200000
-
-/* NDS32 Data Local Memory 01 */
-#define CONFIG_NDS_DLM1_BASE 0x90300000
-/* NDS32 Data Local Memory 02 */
-#define CONFIG_NDS_DLM2_BASE 0x90400000
-
-/* Synopsys DWC DDR2/1 Controller */
-#define CONFIG_DWCDDR21MCTL_BASE 0x90500000
-/* DMA Controller */
-#define CONFIG_FTDMAC020_BASE 0x90600000
-/* FTIDE020_S IDE (ATA) Controller */
-#define CONFIG_FTIDE020S_BASE 0x90700000
-/* USB OTG Controller */
-#define CONFIG_FZOTG266HD0A_BASE 0x90800000
-/* Andes L2 Cache Controller */
-#define CONFIG_NCEL2C100_BASE 0x90900000
-/* XGI XG22 GPU */
-#define CONFIG_XGI_XG22_BASE 0x90A00000
-/* GMAC Ethernet Controller */
-#define CONFIG_FTGMAC100_BASE 0x90B00000
-/* AHB Controller */
-#define CONFIG_FTAHBC020S_BASE 0x90C00000
-/* AHB-to-APB Bridge Controller */
-#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000
-/* External AHB2AHB Controller */
-#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000
-/* Andes Multi-core Interrupt Controller */
-#define CONFIG_NCEMIC100_BASE 0x90F00000
-
-/*
- * APB Device definitions
- */
-/* Compat Flash Controller */
-#define CONFIG_FTCFC010_BASE 0x94000000
-/* APB - SSP (SPI) (without AC97) Controller */
-#define CONFIG_FTSSP010_01_BASE 0x94100000
-/* UART1 - APB STUART Controller (UART0 in Linux) */
-#define CONFIG_FTUART010_01_BASE 0x94200000
-/* APB - SSP with HDA/AC97 Controller */
-#define CONFIG_FTSSP010_02_BASE 0x94500000
-/* UART2 - APB STUART Controller (UART1 in Linux) */
-#define CONFIG_FTUART010_02_BASE 0x94600000
-/* PCU Controller */
-#define CONFIG_ANDES_PCU_BASE 0x94800000
-/* FTTMR010 Timer */
-#define CONFIG_FTTMR010_BASE 0x94900000
-/* Watch Dog Controller */
-#define CONFIG_FTWDT010_BASE 0x94A00000
-/* FTRTC010 Real Time Clock */
-#define CONFIG_FTRTC010_BASE 0x98B00000
-/* GPIO Controller */
-#define CONFIG_FTGPIO010_BASE 0x94C00000
-/* I2C Controller */
-#define CONFIG_FTIIC010_BASE 0x94E00000
-/* PWM - Pulse Width Modulator Controller */
-#define CONFIG_FTPWM010_BASE 0x94F00000
-
-/* Power Management Unit */
-#define CONFIG_FTPMU010_BASE 0x98100000
-
-#endif /* __AG102_H */
+++ /dev/null
-/*
- * Copyright 1995, Russell King.
- * Various bits and pieces copyrights include:
- * Linus Torvalds (test_bit).
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- *
- * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
- *
- * Please note that the code in this file should never be included
- * from user space. Many of these are not implemented in assembler
- * since they would be too costly. Also, they require priviledged
- * instructions (which are not available from user mode) to ensure
- * that they are atomic.
- */
-
-#ifndef __ASM_NDS_BITOPS_H
-#define __ASM_NDS_BITOPS_H
-
-#ifdef __KERNEL__
-
-#include <asm/system.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#define smp_mb__before_clear_bit() do { } while (0)
-#define smp_mb__after_clear_bit() do { } while (0)
-
-/*
- * Function prototypes to keep gcc -Wall happy.
- */
-extern void set_bit(int nr, void *addr);
-
-static inline void __set_bit(int nr, void *addr)
-{
- int *a = (int *)addr;
- int mask;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- *a |= mask;
-}
-
-#define PLATFORM__SET_BIT
-
-extern void clear_bit(int nr, void *addr);
-
-static inline void __clear_bit(int nr, void *addr)
-{
- int *a = (int *)addr;
- int mask;
- unsigned long flags;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- local_irq_save(flags);
- *a &= ~mask;
- local_irq_restore(flags);
-}
-
-#define PLATFORM__CLEAR_BIT
-
-extern void change_bit(int nr, void *addr);
-
-static inline void __change_bit(int nr, void *addr)
-{
- int mask;
- unsigned long *ADDR = (unsigned long *)addr;
-
- ADDR += nr >> 5;
- mask = 1 << (nr & 31);
- *ADDR ^= mask;
-}
-
-extern int test_and_set_bit(int nr, void *addr);
-
-static inline int __test_and_set_bit(int nr, void *addr)
-{
- int mask, retval;
- unsigned int *a = (unsigned int *)addr;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- retval = (mask & *a) != 0;
- *a |= mask;
- return retval;
-}
-
-extern int test_and_clear_bit(int nr, void *addr);
-
-static inline int __test_and_clear_bit(int nr, void *addr)
-{
- int mask, retval;
- unsigned int *a = (unsigned int *)addr;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- retval = (mask & *a) != 0;
- *a &= ~mask;
- return retval;
-}
-
-extern int test_and_change_bit(int nr, void *addr);
-
-static inline int __test_and_change_bit(int nr, void *addr)
-{
- int mask, retval;
- unsigned int *a = (unsigned int *)addr;
-
- a += nr >> 5;
- mask = 1 << (nr & 0x1f);
- retval = (mask & *a) != 0;
- *a ^= mask;
- return retval;
-}
-
-extern int find_first_zero_bit(void *addr, unsigned size);
-extern int find_next_zero_bit(void *addr, int size, int offset);
-
-/*
- * This routine doesn't need to be atomic.
- */
-static inline int test_bit(int nr, const void *addr)
-{
- return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7));
-}
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static inline unsigned long ffz(unsigned long word)
-{
- int k;
-
- word = ~word;
- k = 31;
- if (word & 0x0000ffff) {
- k -= 16; word <<= 16;
- }
- if (word & 0x00ff0000) {
- k -= 8; word <<= 8;
- }
- if (word & 0x0f000000) {
- k -= 4; word <<= 4;
- }
- if (word & 0x30000000) {
- k -= 2; word <<= 2;
- }
- if (word & 0x40000000)
- k -= 1;
-
- return k;
-}
-
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-
-/*
- * redefined in include/linux/bitops.h
- * #define ffs(x) generic_ffs(x)
- */
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-#define hweight32(x) generic_hweight32(x)
-#define hweight16(x) generic_hweight16(x)
-#define hweight8(x) generic_hweight8(x)
-
-#define ext2_set_bit test_and_set_bit
-#define ext2_clear_bit test_and_clear_bit
-#define ext2_test_bit test_bit
-#define ext2_find_first_zero_bit find_first_zero_bit
-#define ext2_find_next_zero_bit find_next_zero_bit
-
-/* Bitmap functions for the minix filesystem. */
-#define minix_test_and_set_bit(nr, addr) test_and_set_bit(nr, addr)
-#define minix_set_bit(nr, addr) set_bit(nr, addr)
-#define minix_test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr)
-#define minix_test_bit(nr, addr) test_bit(nr, addr)
-#define minix_find_first_zero_bit(addr, size) find_first_zero_bit(addr, size)
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASM_NDS_BITOPS_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2013, Google Inc.
- *
- * Copyright (C) 2011
- * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
- */
-#ifndef NDS32_BOOTM_H
-#define NDS32_BOOTM_H
-
-#include <asm/setup.h>
-
-extern void udc_disconnect(void);
-
-#ifdef CONFIG_SUPPORT_PASSING_ATAGS
-# define BOOTM_ENABLE_TAGS 1
-#else
-# define BOOTM_ENABLE_TAGS 0
-#endif
-
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-# define BOOTM_ENABLE_MEMORY_TAGS 1
-#else
-# define BOOTM_ENABLE_MEMORY_TAGS 0
-#endif
-
-#ifdef CONFIG_CMDLINE_TAG
- #define BOOTM_ENABLE_CMDLINE_TAG 1
-#else
- #define BOOTM_ENABLE_CMDLINE_TAG 0
-#endif
-
-#ifdef CONFIG_INITRD_TAG
- #define BOOTM_ENABLE_INITRD_TAG 1
-#else
- #define BOOTM_ENABLE_INITRD_TAG 0
-#endif
-
-#ifdef CONFIG_SERIAL_TAG
- #define BOOTM_ENABLE_SERIAL_TAG 1
-void get_board_serial(struct tag_serialnr *serialnr);
-#else
- #define BOOTM_ENABLE_SERIAL_TAG 0
-static inline void get_board_serial(struct tag_serialnr *serialnr)
-{
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
- #define BOOTM_ENABLE_REVISION_TAG 1
-u32 get_board_rev(void);
-#else
- #define BOOTM_ENABLE_REVISION_TAG 0
-static inline u32 get_board_rev(void)
-{
- return 0;
-}
-#endif
-
-#endif
+++ /dev/null
-/*
- * linux/include/asm-arm/byteorder.h
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- *
- * ARM Endian-ness. In little endian mode, the data bus is connected such
- * that byte accesses appear as:
- * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
- * and word accesses (data or instruction) appear as:
- * d0...d31
- *
- * When in big endian mode, byte accesses appear as:
- * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
- * and word accesses (data or instruction) appear as:
- * d0...d31
- */
-
-#ifndef __ASM_NDS_BYTEORDER_H
-#define __ASM_NDS_BYTEORDER_H
-
-#include <asm/types.h>
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-# define __BYTEORDER_HAS_U64__
-# define __SWAB_64_THRU_32__
-#endif
-
-#ifdef __NDSEB__
-#include <linux/byteorder/big_endian.h>
-#else
-#include <linux/byteorder/little_endian.h>
-#endif
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef _ASM_CACHE_H
-#define _ASM_CACHE_H
-
-/* cache */
-int icache_status(void);
-void icache_enable(void);
-void icache_disable(void);
-int dcache_status(void);
-void dcache_enable(void);
-void dcache_disable(void);
-void cache_flush(void);
-
-#define DEFINE_GET_SYS_REG(reg) \
- static inline unsigned long GET_##reg(void) \
- { \
- unsigned long val; \
- __asm__ volatile ( \
- "mfsr %0, $"#reg : "=&r" (val) : : "memory" \
- ); \
- return val; \
- }
-
-enum cache_t {ICACHE, DCACHE};
-DEFINE_GET_SYS_REG(ICM_CFG);
-DEFINE_GET_SYS_REG(DCM_CFG);
-/* I-cache sets (# of cache lines) per way */
-#define ICM_CFG_OFF_ISET 0
-/* I-cache ways */
-#define ICM_CFG_OFF_IWAY 3
-#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET)
-#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY)
-/* D-cache sets (# of cache lines) per way */
-#define DCM_CFG_OFF_DSET 0
-/* D-cache ways */
-#define DCM_CFG_OFF_DWAY 3
-#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET)
-#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY)
-/* I-cache line size */
-#define ICM_CFG_OFF_ISZ 6
-#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ)
-/* D-cache line size */
-#define DCM_CFG_OFF_DSZ 6
-#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
-
-/*
- * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
- * We use that value for aligning DMA buffers unless the board config has
- * specified an alternate cache line size.
- */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN 32
-#endif
-
-#endif /* _ASM_CACHE_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
- * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
- */
-
-#ifndef _ASM_CONFIG_H_
-#define _ASM_CONFIG_H_
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Andes Technology Corporation
- * Ken Kuo, Andes Technology Corporation <ken_kuo@andestech.com>
- */
-#ifndef __ASM_NDS_DMA_MAPPING_H
-#define __ASM_NDS_DMA_MAPPING_H
-
-#include <common.h>
-#include <asm/cache.h>
-#include <cpu_func.h>
-#include <linux/dma-direction.h>
-#include <linux/types.h>
-#include <malloc.h>
-
-static void *dma_alloc_coherent(size_t len, unsigned long *handle)
-{
- *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
- return (void *)*handle;
-}
-
-#endif /* __ASM_NDS_DMA_MAPPING_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-/**************************************************************
- * CAUTION:
- * - do not implement for NDS32 Arch yet.
- * - so far no one uses the macros defined in this head file.
- **************************************************************/
-
-#ifndef __ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include <config.h>
-
-/* Architecture-specific global data */
-struct arch_global_data {
-};
-
-#include <asm-generic/global_data.h>
-
-#ifdef CONFIG_GLOBAL_DATA_NOT_REG10
-extern volatile gd_t g_gd;
-#define DECLARE_GLOBAL_DATA_PTR static volatile gd_t *gd = &g_gd
-#else
-#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("$r10")
-#endif
-
-#endif /* __ASM_GBL_DATA_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/include/asm-nds/io.h
- *
- * Copyright (C) 1996-2000 Russell King
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- *
- * Modifications:
- * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
- * constant addresses and variable addresses.
- * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
- * specific IO header files.
- * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
- * 04-Apr-1999 PJB Added check_signature.
- * 12-Dec-1999 RMK More cleanups
- * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
- */
-#ifndef __ASM_NDS_IO_H
-#define __ASM_NDS_IO_H
-
-/*
- * CAUTION:
- * - do not implement for NDS32 Arch yet.
- * - cmd_pci.c, cmd_scsi.c, Lynxkdi.c, usb.c, usb_storage.c, etc...
- * iinclude asm/io.h
- */
-
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-#include <asm/byteorder.h>
-
-static inline void sync(void)
-{
-}
-
-#ifdef CONFIG_ARCH_MAP_SYSMEM
-static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
-{
- if(paddr <PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)
- paddr = paddr | 0x40000000;
- return (void *)(uintptr_t)paddr;
-}
-
-static inline void *unmap_sysmem(const void *vaddr)
-{
- phys_addr_t paddr = (phys_addr_t)vaddr;
- paddr = paddr & ~0x40000000;
- return (void *)(uintptr_t)paddr;
-}
-
-static inline phys_addr_t map_to_sysmem(const void *ptr)
-{
- return (phys_addr_t)(uintptr_t)ptr;
-}
-#endif
-
-/*
- * Generic virtual read/write. Note that we don't support half-word
- * read/writes. We define __arch_*[bl] here, and leave __arch_*w
- * to the architecture specific code.
- */
-#define __arch_getb(a) (*(unsigned char *)(a))
-#define __arch_getw(a) (*(unsigned short *)(a))
-#define __arch_getl(a) (*(unsigned int *)(a))
-
-#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
-#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
-#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
-
-extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
-extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
-extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
-
-extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
-extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
-extern void __raw_readsl(unsigned int addr, void *data, int longlen);
-
-#define __raw_writeb(v, a) __arch_putb(v, a)
-#define __raw_writew(v, a) __arch_putw(v, a)
-#define __raw_writel(v, a) __arch_putl(v, a)
-
-#define __raw_readb(a) __arch_getb(a)
-#define __raw_readw(a) __arch_getw(a)
-#define __raw_readl(a) __arch_getl(a)
-
-/*
- * TODO: The kernel offers some more advanced versions of barriers, it might
- * have some advantages to use them instead of the simple one here.
- */
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
-#define __iormb() dmb()
-#define __iowmb() dmb()
-
-static inline void writeb(u8 val, volatile void __iomem *addr)
-{
- __iowmb();
- __arch_putb(val, addr);
-}
-
-static inline void writew(u16 val, volatile void __iomem *addr)
-{
- __iowmb();
- __arch_putw(val, addr);
-
-}
-
-static inline void writel(u32 val, volatile void __iomem *addr)
-{
- __iowmb();
- __arch_putl(val, addr);
-}
-
-static inline u8 readb(const volatile void __iomem *addr)
-{
- u8 val;
-
- val = __arch_getb(addr);
- __iormb();
- return val;
-}
-
-static inline u16 readw(const volatile void __iomem *addr)
-{
- u16 val;
-
- val = __arch_getw(addr);
- __iormb();
- return val;
-}
-
-static inline u32 readl(const volatile void __iomem *addr)
-{
- u32 val;
-
- val = __arch_getl(addr);
- __iormb();
- return val;
-}
-
-/*
- * The compiler seems to be incapable of optimising constants
- * properly. Spell it out to the compiler in some cases.
- * These are only valid for small values of "off" (< 1<<12)
- */
-#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off)
-#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off)
-#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off)
-
-#define __raw_base_readb(base, off) __arch_base_getb(base, off)
-#define __raw_base_readw(base, off) __arch_base_getw(base, off)
-#define __raw_base_readl(base, off) __arch_base_getl(base, off)
-
-#define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
-#define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
-
-#define out_le32(a, v) out_arch(l, le32, a, v)
-#define out_le16(a, v) out_arch(w, le16, a, v)
-
-#define in_le32(a) in_arch(l, le32, a)
-#define in_le16(a) in_arch(w, le16, a)
-
-#define out_be32(a, v) out_arch(l, be32, a, v)
-#define out_be16(a, v) out_arch(w, be16, a, v)
-
-#define in_be32(a) in_arch(l, be32, a)
-#define in_be16(a) in_arch(w, be16, a)
-
-#define out_8(a, v) __raw_writeb(v, a)
-#define in_8(a) __raw_readb(a)
-
-/*
- * Clear and set bits in one shot. These macros can be used to clear and
- * set multiple bits in a register using a single call. These macros can
- * also be used to set a multiple-bit bit pattern using a mask, by
- * specifying the mask in the 'clear' parameter and the new bit pattern
- * in the 'set' parameter.
- */
-
-#define clrbits(type, addr, clear) \
- out_##type((addr), in_##type(addr) & ~(clear))
-
-#define setbits(type, addr, set) \
- out_##type((addr), in_##type(addr) | (set))
-
-#define clrsetbits(type, addr, clear, set) \
- out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
-
-#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
-#define setbits_be32(addr, set) setbits(be32, addr, set)
-#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
-
-#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
-#define setbits_le32(addr, set) setbits(le32, addr, set)
-#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
-
-#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
-#define setbits_be16(addr, set) setbits(be16, addr, set)
-#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
-
-#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
-#define setbits_le16(addr, set) setbits(le16, addr, set)
-#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
-
-#define clrbits_8(addr, clear) clrbits(8, addr, clear)
-#define setbits_8(addr, set) setbits(8, addr, set)
-#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
-
-/*
- * Now, pick up the machine-defined IO definitions
- * #include <asm/arch/io.h>
- */
-
-/*
- * IO port access primitives
- * -------------------------
- *
- * The NDS32 doesn't have special IO access instructions just like ARM;
- * all IO is memory mapped.
- * Note that these are defined to perform little endian accesses
- * only. Their primary purpose is to access PCI and ISA peripherals.
- *
- * Note that for a big endian machine, this implies that the following
- * big endian mode connectivity is in place, as described by numerious
- * ARM documents:
- *
- * PCI: D0-D7 D8-D15 D16-D23 D24-D31
- * ARM: D24-D31 D16-D23 D8-D15 D0-D7
- *
- * The machine specific io.h include defines __io to translate an "IO"
- * address to a memory address.
- *
- * Note that we prevent GCC re-ordering or caching values in expressions
- * by introducing sequence points into the in*() definitions. Note that
- * __raw_* do not guarantee this behaviour.
- *
- * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
- */
-#ifdef __io
-#define outb(v, p) __raw_writeb(v, __io(p))
-#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
-#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
-
-#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
-#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
-#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
-
-#define outsb(p, d, l) writesb(__io(p), d, l)
-#define outsw(p, d, l) writesw(__io(p), d, l)
-#define outsl(p, d, l) writesl(__io(p), d, l)
-
-#define insb(p, d, l) readsb(__io(p), d, l)
-#define insw(p, d, l) readsw(__io(p), d, l)
-#define insl(p, d, l) readsl(__io(p), d, l)
-
-static inline void readsb(unsigned int *addr, void * data, int bytelen)
-{
- unsigned char *ptr = (unsigned char *)addr;
- unsigned char *ptr2 = (unsigned char *)data;
- while (bytelen) {
- *ptr2 = *ptr;
- ptr2++;
- bytelen--;
- }
-}
-
-static inline void readsw(unsigned int *addr, void * data, int wordlen)
-{
- unsigned short *ptr = (unsigned short *)addr;
- unsigned short *ptr2 = (unsigned short *)data;
- while (wordlen) {
- *ptr2 = *ptr;
- ptr2++;
- wordlen--;
- }
-}
-
-static inline void readsl(unsigned int *addr, void * data, int longlen)
-{
- unsigned int *ptr = (unsigned int *)addr;
- unsigned int *ptr2 = (unsigned int *)data;
- while (longlen) {
- *ptr2 = *ptr;
- ptr2++;
- longlen--;
- }
-}
-static inline void writesb(unsigned int *addr, const void * data, int bytelen)
-{
- unsigned char *ptr = (unsigned char *)addr;
- unsigned char *ptr2 = (unsigned char *)data;
- while (bytelen) {
- *ptr = *ptr2;
- ptr2++;
- bytelen--;
- }
-}
-static inline void writesw(unsigned int *addr, const void * data, int wordlen)
-{
- unsigned short *ptr = (unsigned short *)addr;
- unsigned short *ptr2 = (unsigned short *)data;
- while (wordlen) {
- *ptr = *ptr2;
- ptr2++;
- wordlen--;
- }
-}
-static inline void writesl(unsigned int *addr, const void * data, int longlen)
-{
- unsigned int *ptr = (unsigned int *)addr;
- unsigned int *ptr2 = (unsigned int *)data;
- while (longlen) {
- *ptr = *ptr2;
- ptr2++;
- longlen--;
- }
-}
-#endif
-
-#define outb_p(val, port) outb((val), (port))
-#define outw_p(val, port) outw((val), (port))
-#define outl_p(val, port) outl((val), (port))
-#define inb_p(port) inb((port))
-#define inw_p(port) inw((port))
-#define inl_p(port) inl((port))
-
-#define outsb_p(port, from, len) outsb(port, from, len)
-#define outsw_p(port, from, len) outsw(port, from, len)
-#define outsl_p(port, from, len) outsl(port, from, len)
-#define insb_p(port, to, len) insb(port, to, len)
-#define insw_p(port, to, len) insw(port, to, len)
-#define insl_p(port, to, len) insl(port, to, len)
-
-/*
- * DMA-consistent mapping functions. These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices. This is the "generic" version. The PCI specific version
- * is in pci.h
- */
-extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
-extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle);
-extern void consistent_sync(void *vaddr, size_t size, int rw);
-
-/*
- * String version of IO memory access ops:
- */
-extern void _memcpy_fromio(void *, unsigned long, size_t);
-extern void _memcpy_toio(unsigned long, const void *, size_t);
-extern void _memset_io(unsigned long, int, size_t);
-
-extern void __readwrite_bug(const char *fn);
-
-/*
- * If this architecture has PCI memory IO, then define the read/write
- * macros. These should only be used with the cookie passed from
- * ioremap.
- */
-#ifdef __mem_pci
-
-#define readb(c) ({ unsigned int __v = \
- __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ unsigned int __v = \
- le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ unsigned int __v = \
- le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
-
-#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
-#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
-#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
-
-#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
-#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
-#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
-
-#define eth_io_copy_and_sum(s, c, l, b) \
- eth_copy_and_sum((s), __mem_pci(c), (l), (b))
-
-static inline int
-check_signature(unsigned long io_addr, const unsigned char *signature,
- int length)
-{
- int retval = 0;
- do {
- if (readb(io_addr) != *signature)
- goto out;
- io_addr++;
- signature++;
- length--;
- } while (length);
- retval = 1;
-out:
- return retval;
-}
-#endif /* __mem_pci */
-
-/*
- * If this architecture has ISA IO, then define the isa_read/isa_write
- * macros.
- */
-#ifdef __mem_isa
-
-#define isa_readb(addr) __raw_readb(__mem_isa(addr))
-#define isa_readw(addr) __raw_readw(__mem_isa(addr))
-#define isa_readl(addr) __raw_readl(__mem_isa(addr))
-#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr))
-#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr))
-#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr))
-#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c))
-#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c))
-#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c))
-
-#define isa_eth_io_copy_and_sum(a, b, c, d) \
- eth_copy_and_sum((a), __mem_isa(b), (c), (d))
-
-static inline int
-isa_check_signature(unsigned long io_addr, const unsigned char *signature,
- int length)
-{
- int retval = 0;
- do {
- if (isa_readb(io_addr) != *signature)
- goto out;
- io_addr++;
- signature++;
- length--;
- } while (length);
- retval = 1;
-out:
- return retval;
-}
-
-#else /* __mem_isa */
-
-#define isa_readb(addr) (__readwrite_bug("isa_readb"), 0)
-#define isa_readw(addr) (__readwrite_bug("isa_readw"), 0)
-#define isa_readl(addr) (__readwrite_bug("isa_readl"), 0)
-#define isa_writeb(val, addr) __readwrite_bug("isa_writeb")
-#define isa_writew(val, addr) __readwrite_bug("isa_writew")
-#define isa_writel(val, addr) __readwrite_bug("isa_writel")
-#define isa_memset_io(a, b, c) __readwrite_bug("isa_memset_io")
-#define isa_memcpy_fromio(a, b, c) __readwrite_bug("isa_memcpy_fromio")
-#define isa_memcpy_toio(a, b, c) __readwrite_bug("isa_memcpy_toio")
-
-#define isa_eth_io_copy_and_sum(a, b, c, d) \
- __readwrite_bug("isa_eth_io_copy_and_sum")
-
-#define isa_check_signature(io, sig, len) (0)
-
-#endif /* __mem_isa */
-
-#include <asm-generic/io.h>
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_NDS_IO_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * U-Boot - linkage.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#endif
+++ /dev/null
-/*
- * This was automagically generated from arch/nds/tools/mach-types!
- * Do NOT edit
- */
-
-#ifndef __ASM_NDS32_MACH_TYPE_H
-#define __ASM_NDS32_MACH_TYPE_H
-
-#ifndef __ASSEMBLY__
-/* The type of machine we're running on */
-extern unsigned int __machine_arch_type;
-#endif
-
-/* see arch/arm/kernel/arch.c for a description of these */
-#define MACH_TYPE_ADPAG101P 1
-#define MACH_TYPE_ADPAE3XX 2
-
-#ifdef CONFIG_ARCH_ADPAG101P
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_ADPAG101P
-# endif
-# define machine_is_adpag101p() (machine_arch_type == MACH_TYPE_ADPAG101P)
-#else
-# define machine_is_adpag101p() (1)
-#endif
-
-#endif /* __ASM_NDS32_MACH_TYPE_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * include/asm-nds32/macro.h
- *
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __ASM_NDS_MACRO_H
-#define __ASM_NDS_MACRO_H
-#ifdef __ASSEMBLY__
-
-/*
- * These macros provide a convenient way to write 8, 16 and 32 bit data
- * to an "immediate address (address used by periphal)" only.
- * Registers r4 and r5 are used, any data in these registers are
- * overwritten by the macros.
- * The macros are valid for any NDS32 architecture, they do not implement
- * any memory barriers so caution is recommended when using these when the
- * caches are enabled or on a multi-core system.
- */
-
-.macro write32, addr, data
- li $r4, \addr
- li $r5, \data
- swi $r5, [$r4]
-.endm
-
-.macro write16, addr, data
- li $r4, \addr
- li $r5, \data
- shi $r5, [$r4]
-.endm
-
-.macro write8, addr, data
- li $r4, \addr
- li $r5, \data
- sbi $r5, [$r4]
-.endm
-
-/*
- * This macro read a value from a register, then do OR operation
- * (set bit fields) to the value, and then store it back to the register.
- * Note: Instruction 'ori' supports immediate value up to 15 bits.
- */
-.macro setbf32, addr, data
- li $r4, \addr
- lwi $r5, [$r4]
- li $r6, \data
- or $r5, $r5, $r6
- swi $r5, [$r4]
-.endm
-
-.macro setbf15, addr, data
- li $r4, \addr
- lwi $r5, [$r4]
- ori $r5, $r5, \data
- swi $r5, [$r4]
-.endm
-
-/*
- * This macro generates a loop that can be used for delays in the code.
- * Register r4 is used, any data in this register is overwritten by the
- * macro.
- * The macro is valid for any NDS32 architeture. The actual time spent in the
- * loop will vary from CPU to CPU though.
- */
-
-.macro wait_timer, time
- li $r4, \time
-1:
- nop
- addi $r4, $r4, -1
- bnez $r4, 1b
-.endm
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARM_MACRO_H */
+++ /dev/null
-/*
- * linux/include/asm-arm/posix_types.h
- *
- * Copyright (C) 1996-1998 Russell King.
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
- * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Changelog:
- * 27-06-1996 RMK Created
- * 05-03-2010 Modified for arch NDS32
- */
-#ifndef __ARCH_NDS_POSIX_TYPES_H
-#define __ARCH_NDS_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc. Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned short __kernel_dev_t;
-typedef unsigned long __kernel_ino_t;
-typedef unsigned short __kernel_mode_t;
-typedef unsigned short __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef int __kernel_pid_t;
-typedef unsigned short __kernel_ipc_pid_t;
-typedef unsigned short __kernel_uid_t;
-typedef unsigned short __kernel_gid_t;
-#ifdef __GNUC__
-typedef __SIZE_TYPE__ __kernel_size_t;
-#else
-typedef unsigned int __kernel_size_t;
-#endif
-typedef int __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
- int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
-
-#undef __FD_SET
-#define __FD_SET(fd, fdsetp) \
- (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31)))
-
-#undef __FD_CLR
-#define __FD_CLR(fd, fdsetp) \
- (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31)))
-
-#undef __FD_ISSET
-#define __FD_ISSET(fd, fdsetp) \
- ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0)
-
-#undef __FD_ZERO
-#define __FD_ZERO(fdsetp) \
- (memset(fdsetp, 0, sizeof(*(fd_set *) fdsetp)))
-
-#endif
-
-#endif /* __ARCH_NDS_POSIX_TYPES_H */
+++ /dev/null
-/*
- * linux/include/asm-arm/processor.h
- *
- * Copyright (C) 1995-2002 Russell King
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
- * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_NDS_PROCESSOR_H
-#define __ASM_NDS_PROCESSOR_H
-
-/**************************************************************
- * CAUTION:
- * - do not implement for NDS32 Arch yet.
- * - so far some files include /asm/processor.h, but
- * no one uses the macros defined in this head file.
- **************************************************************/
-
-#endif /* __ASM_ARM_PROCESSOR_H */
+++ /dev/null
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
- * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_NDS_PTRACE_H
-#define __ASM_NDS_PTRACE_H
-
-#define USR_MODE 0x00
-#define SU_MODE 0x01
-#define HV_MODE 0x10
-#define MODE_MASK (0x03<<3)
-#define GIE_BIT 0x01
-
-#ifndef __ASSEMBLY__
-
-/* this struct defines the way the registers are stored on the
- stack during a system call. */
-
-#define NDS32_REG long
-
-struct pt_regs {
- NDS32_REG ir0;
- NDS32_REG ipsw;
- NDS32_REG ipc;
- NDS32_REG sp;
- NDS32_REG orig_r0;
- NDS32_REG pipsw;
- NDS32_REG pipc;
- NDS32_REG pp0;
- NDS32_REG pp1;
- NDS32_REG d0hi;
- NDS32_REG d0lo;
- NDS32_REG d1hi;
- NDS32_REG d1lo;
- NDS32_REG r[26]; /* r0 - r25 */
- NDS32_REG p0; /* r26 - used by OS */
- NDS32_REG p1; /* r27 - used by OS */
- NDS32_REG fp; /* r28 */
- NDS32_REG gp; /* r29 */
- NDS32_REG lp; /* r30 */
- NDS32_REG fucop_ctl;
- NDS32_REG osp;
-};
-
-#define processor_mode(regs) \
- (((regs)->ipsw & MODE_MASK) >> 3)
-
-#define interrupts_enabled(regs) \
- ((regs)->ipsw & GIE_BIT)
-
-/*
- * Offsets used by 'ptrace' system call interface.
- * These can't be changed without breaking binary compatibility
- * with MkLinux, etc.
- */
-#define PT_R0 0
-#define PT_R1 1
-#define PT_R2 2
-#define PT_R3 3
-#define PT_R4 4
-#define PT_R5 5
-#define PT_R6 6
-#define PT_R7 7
-#define PT_R8 8
-#define PT_R9 9
-#define PT_R10 10
-#define PT_R11 11
-#define PT_R12 12
-#define PT_R13 13
-#define PT_R14 14
-#define PT_R15 15
-#define PT_R16 16
-#define PT_R17 17
-#define PT_R18 18
-#define PT_R19 19
-#define PT_R20 20
-#define PT_R21 21
-#define PT_R22 22
-#define PT_R23 23
-#define PT_R24 24
-#define PT_R25 25
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_NDS_PTRACE_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2012 The Chromium OS Authors.
- */
-
-#ifndef __ASM_NDS32_SECTIONS_H
-#define __ASM_NDS32_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * linux/arch/nds32/include/asm/setup.h
- *
- * Copyright (C) 1997-1999 Russell King
- * Copyright (C) 2008 Andes Technology Corporation
- * Copyright (C) 2013 Ken Kuo (ken_kuo@andestech.com)
- *
- * Structure passed to kernel to tell it about the
- * hardware it's running on. See Documentation/arm/Setup
- * for more info.
- */
-#ifndef __ASMNDS32_SETUP_H
-#define __ASMNDS32_SETUP_H
-
-#define COMMAND_LINE_SIZE 256
-
-/* The list ends with an ATAG_NONE node. */
-#define ATAG_NONE 0x00000000
-
-struct tag_header {
- u32 size;
- u32 tag;
-};
-
-/* The list must start with an ATAG_CORE node */
-#define ATAG_CORE 0x54410001
-
-struct tag_core {
- u32 flags; /* bit 0 = read-only */
- u32 pagesize;
- u32 rootdev;
-};
-
-/* it is allowed to have multiple ATAG_MEM nodes */
-#define ATAG_MEM 0x54410002
-
-struct tag_mem32 {
- u32 size;
- u32 start; /* physical start address */
-};
-
-/* VGA text type displays */
-#define ATAG_VIDEOTEXT 0x54410003
-
-struct tag_videotext {
- u8 x;
- u8 y;
- u16 video_page;
- u8 video_mode;
- u8 video_cols;
- u16 video_ega_bx;
- u8 video_lines;
- u8 video_isvga;
- u16 video_points;
-};
-
-/* describes how the ramdisk will be used in kernel */
-#define ATAG_RAMDISK 0x54410004
-
-struct tag_ramdisk {
- u32 flags; /* bit 0 = load, bit 1 = prompt */
- u32 size; /* decompressed ramdisk size in _kilo_ bytes */
- u32 start; /* starting block of floppy-based RAM disk image */
-};
-
-/*
- * this one accidentally used virtual addresses - as such,
- * it's deprecated.
- * describes where the compressed ramdisk image lives (virtual address)
- */
-#define ATAG_INITRD 0x54410005
-
-/* describes where the compressed ramdisk image lives (physical address) */
-#define ATAG_INITRD2 0x54420005
-
-struct tag_initrd {
- u32 start; /* physical start address */
- u32 size; /* size of compressed ramdisk image in bytes */
-};
-
-/* board serial number. "64 bits should be enough for everybody" */
-#define ATAG_SERIAL 0x54410006
-
-struct tag_serialnr {
- u32 low;
- u32 high;
-};
-
-/* board revision */
-#define ATAG_REVISION 0x54410007
-
-struct tag_revision {
- u32 rev;
-};
-
-/* initial values for vesafb-type framebuffers. see struct screen_info
- * in include/linux/tty.h
- */
-#define ATAG_VIDEOLFB 0x54410008
-
-struct tag_videolfb {
- u16 lfb_width;
- u16 lfb_height;
- u16 lfb_depth;
- u16 lfb_linelength;
- u32 lfb_base;
- u32 lfb_size;
- u8 red_size;
- u8 red_pos;
- u8 green_size;
- u8 green_pos;
- u8 blue_size;
- u8 blue_pos;
- u8 rsvd_size;
- u8 rsvd_pos;
-};
-
-/* command line: \0 terminated string */
-#define ATAG_CMDLINE 0x54410009
-
-struct tag_cmdline {
- char cmdline[COMMAND_LINE_SIZE];
-};
-
-struct tag {
- struct tag_header hdr;
- union {
- struct tag_core core;
- struct tag_mem32 mem;
- struct tag_videotext videotext;
- struct tag_ramdisk ramdisk;
- struct tag_initrd initrd;
- struct tag_serialnr serialnr;
- struct tag_revision revision;
- struct tag_videolfb videolfb;
- struct tag_cmdline cmdline;
- } u;
-};
-
-struct tagtable {
- u32 tag;
- int (*parse)(const struct tag *);
-};
-
-#define tag_member_present(tag, member) \
- ((unsigned long)(&((struct tag *)0L)->member + 1) \
- <= (tag)->hdr.size * 4)
-
-#define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size))
-#define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
-
-#define for_each_tag(t, base) \
- for (t = base; t->hdr.size; t = tag_next(t))
-
-#ifdef __KERNEL__
-
-#define __tag __used __section(".taglist")
-#define __tagtable(tag, fn) \
-static struct tagtable __tagtable_##fn __tag = { tag, fn }
-
-/*
- * Memory map description
- */
-#define NR_BANKS 8
-
-struct meminfo {
- int nr_banks;
- struct {
- unsigned long start;
- unsigned long size;
- int node;
- } bank[NR_BANKS];
-};
-
-/*
- * Early command line parameters.
- */
-struct early_params {
- const char *arg;
- void (*fn)(char **p);
-};
-
-#define __early_param(name, fn) \
-static struct early_params __early_##fn __used \
-__section("__early_param") = { name, fn }
-
-#endif
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
- * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef __ASM_NDS_STRING_H
-#define __ASM_NDS_STRING_H
-
-/*
- * We don't do inline string functions, since the
- * optimised inline asm versions are not small.
- */
-
-#undef __HAVE_ARCH_STRRCHR
-extern char *strrchr(const char *s, int c);
-
-#undef __HAVE_ARCH_STRCHR
-extern char *strchr(const char *s, int c);
-
-#undef __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *, const void *, __kernel_size_t);
-
-#undef __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *, const void *, __kernel_size_t);
-
-#undef __HAVE_ARCH_MEMCHR
-extern void *memchr(const void *, int, __kernel_size_t);
-
-#undef __HAVE_ARCH_MEMZERO
-#undef __HAVE_ARCH_MEMSET
-extern void *memset(void *, int, __kernel_size_t);
-
-#ifdef CONFIG_MARCO_MEMSET
-extern void __memzero(void *ptr, __kernel_size_t n);
-
-#define memset(p, v, n) \
- ({ \
- if ((n) != 0) { \
- if (__builtin_constant_p((v)) && (v) == 0) \
- __memzero((p), (n)); \
- else \
- memset((p), (v), (n)); \
- } \
- (p); \
- })
-
-#define memzero(p, n) ({ if ((n) != 0) __memzero((p), (n)); (p); })
-#else
-extern void memzero(void *ptr, __kernel_size_t n);
-#endif
-
-#endif /* __ASM_NDS_STRING_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __ASM_NDS_SYSTEM_H
-#define __ASM_NDS_SYSTEM_H
-
-/*
- * Interrupt configuring macros.
- */
-
-extern int irq_flags;
-
-#define local_irq_enable() \
- __asm__ __volatile__ ( \
- "mfsr %0, $psw\n\t" \
- "andi %0, %0, 0x1\n\t" \
- "setgie.e\n\t" \
- : \
- : "r" (irq_flags) \
- )
-
-#define local_irq_disable() \
- do { \
- int __tmp_dummy; \
- __asm__ __volatile__ ( \
- "mfsr %0, $psw\n\t" \
- "andi %0, %0, 0x1\n\t" \
- "setgie.d\n\t" \
- "dsb\n\t" \
- : "=r" (__tmp_dummy) \
- ); \
- } while (0)
-
-#define local_irq_save(x) \
- __asm__ __volatile__ ( \
- "mfsr %0, $psw\n\t" \
- "andi %0, %0, 0x1\n\t" \
- "setgie.d\n\t" \
- "dsb\n\t" \
- : "=&r" (x) \
- )
-
-#define local_save_flags(x) \
- __asm__ __volatile__ ( \
- "mfsr %0, $psw\n\t" \
- "andi %0, %0, 0x1\n\t" \
- "setgie.e\n\t" \
- "setgie.d\n\t" \
- : "=r" (x) \
- )
-
-#define irqs_enabled_from_flags(x) ((x) != 0x1f)
-
-#define local_irq_restore(x) \
- do { \
- if (irqs_enabled_from_flags(x)) \
- local_irq_enable(); \
- } while (0)
-
-/*
- * Force strict CPU ordering.
- */
-#define nop() asm volatile ("nop;\n\t" : : )
-#define mb() asm volatile ("" : : : "memory")
-#define rmb() asm volatile ("" : : : "memory")
-#define wmb() asm volatile ("" : : : "memory")
-
-#endif /* __ASM_NDS_SYSTEM_H */
+++ /dev/null
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
- * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef __ASM_NDS_TYPES_H
-#define __ASM_NDS_TYPES_H
-
-#include <asm-generic/int-ll64.h>
-
-typedef unsigned short umode_t;
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#include <stddef.h>
-
-typedef u32 dma_addr_t;
-
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
-
-#endif /* __KERNEL__ */
-
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef _U_BOOT_NDS32_H_
-#define _U_BOOT_NDS32_H_ 1
-
-#include <linux/types.h>
-
-/* for the following variables, see start.S */
-extern ulong IRQ_STACK_START; /* top of IRQ stack */
-extern ulong FIQ_STACK_START; /* top of FIQ stack */
-
-/* cpu/.../cpu.c */
-int cleanup_before_linux(void);
-
-/* board/.../... */
-int board_init(void);
-
-/* cpu/.../interrupt.c */
-void reset_timer_masked(void);
-
-#endif /* _U_BOOT_NDS32_H_ */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Copyright (C) 2010 Shawn Lin (nobuhiro@andestech.com)
- * Copyright (C) 2011 Macpaul Lin (macpaul@andestech.com)
- *
- ********************************************************************
- * NOTE: This header file defines an interface to U-Boot. Including
- * this (unmodified) header file in another file is considered normal
- * use of U-Boot, and does *not* fall under the heading of "derived
- * work".
- ********************************************************************
- */
-
-#ifndef _U_BOOT_H_
-#define _U_BOOT_H_ 1
-
-/* Use the generic board which requires a unified bd_info */
-#include <asm-generic/u-boot.h>
-#include <asm/u-boot-nds32.h>
-
-/* For image.h:image_check_target_arch() */
-#define IH_ARCH_DEFAULT IH_ARCH_NDS32
-
-#endif /* _U_BOOT_H_ */
+++ /dev/null
-#include <asm-generic/unaligned.h>
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2011 Andes Technology Corporation
-# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
-# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
-
-obj-y += cache.o
-obj-$(CONFIG_CMD_BOOTM) += bootm.o
-obj-$(CONFIG_CMD_GO) += boot.o
-obj-y += interrupts.o
+++ /dev/null
-/*
- * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
- *
- * Generate definitions needed by assembly language modules.
- * This code generates raw asm output which is post-processed to extract
- * and format the required data.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <common.h>
-
-#include <linux/kbuild.h>
-
-int main(void)
-{
- /*
- * TODO : Check if each entry in this file is really necessary.
- * - struct ftahbc02s
- * - struct ftsdmc021
- * - struct andes_pcu
- * - struct dwcddr21mctl
- * are used only for generating asm-offsets.h.
- * It means their offset addresses are referenced only from assembly
- * code. Is it better to define the macros directly in headers?
- */
-
-#ifdef CONFIG_FTSMC020
- OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
- OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
-#endif
- BLANK();
-#ifdef CONFIG_FTAHBC020S
- OFFSET(FTAHBC020S_SLAVE_BSR_4, ftahbc02s, s_bsr[4]);
- OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
- OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
-#endif
- BLANK();
-#ifdef CONFIG_FTPMU010
- OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
-#endif
- BLANK();
-#ifdef CONFIG_FTSDMC021
- OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
- OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
- OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
- OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
- OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
- OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
- OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
- OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
-#endif
- BLANK();
-#ifdef CONFIG_ANDES_PCU
- OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
-#endif
- BLANK();
-#ifdef CONFIG_DWCDDR21MCTL
- OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
- OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
- OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
- OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
- OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
- OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
- OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
- OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
- OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
- OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
- OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
- OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
- OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
- OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
- OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
- OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
- OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
- OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
- OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
-#endif
-
- return 0;
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-
-
-#include <common.h>
-#include <command.h>
-
-unsigned long do_go_exec(ulong (*entry)(int, char * const []),
- int argc, char *const argv[])
-{
- cleanup_before_linux();
-
- return entry(argc, argv);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#include <common.h>
-#include <bootstage.h>
-#include <command.h>
-#include <env.h>
-#include <hang.h>
-#include <image.h>
-#include <log.h>
-#include <asm/global_data.h>
-#include <u-boot/zlib.h>
-#include <asm/byteorder.h>
-#include <asm/bootm.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SUPPORT_PASSING_ATAGS
-static void setup_start_tag(struct bd_info *bd);
-
-# ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags(struct bd_info *bd);
-# endif
-static void setup_commandline_tag(struct bd_info *bd, char *commandline);
-
-# ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag(struct bd_info *bd, ulong initrd_start,
- ulong initrd_end);
-# endif
-static void setup_end_tag(struct bd_info *bd);
-
-static struct tag *params;
-#endif /* CONFIG_SUPPORT_PASSING_ATAGS */
-
-int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
-{
- struct bd_info *bd = gd->bd;
- char *s;
- int machid = bd->bi_arch_number;
- void (*theKernel)(int zero, int arch, uint params);
-
-#ifdef CONFIG_CMDLINE_TAG
- char *commandline = env_get("bootargs");
-#endif
-
- /*
- * allow the PREP bootm subcommand, it is required for bootm to work
- */
- if (flag & BOOTM_STATE_OS_PREP)
- return 0;
-
- if ((flag != 0) && (flag != BOOTM_STATE_OS_GO))
- return 1;
-
- theKernel = (void (*)(int, int, uint))images->ep;
-
- s = env_get("machid");
- if (s) {
- machid = hextoul(s, NULL);
- printf("Using machid 0x%x from environment\n", machid);
- }
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- debug("## Transferring control to Linux (at address %08lx) ...\n",
- (ulong)theKernel);
-
- if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len) {
-#ifdef CONFIG_OF_LIBFDT
- debug("using: FDT\n");
- if (image_setup_linux(images)) {
- printf("FDT creation failed! hanging...");
- hang();
- }
-#endif
- } else if (BOOTM_ENABLE_TAGS) {
-#ifdef CONFIG_SUPPORT_PASSING_ATAGS
- setup_start_tag(bd);
-#ifdef CONFIG_SERIAL_TAG
- setup_serial_tag(¶ms);
-#endif
-#ifdef CONFIG_REVISION_TAG
- setup_revision_tag(¶ms);
-#endif
-#ifdef CONFIG_SETUP_MEMORY_TAGS
- setup_memory_tags(bd);
-#endif
-#ifdef CONFIG_CMDLINE_TAG
- setup_commandline_tag(bd, commandline);
-#endif
-#ifdef CONFIG_INITRD_TAG
- if (images->rd_start && images->rd_end)
- setup_initrd_tag(bd, images->rd_start, images->rd_end);
-#endif
- setup_end_tag(bd);
-#endif
-
- /* we assume that the kernel is in place */
- printf("\nStarting kernel ...\n\n");
-
-#ifdef CONFIG_USB_DEVICE
- {
- extern void udc_disconnect(void);
- udc_disconnect();
- }
-#endif
- }
- cleanup_before_linux();
- if (CONFIG_IS_ENABLED(OF_LIBFDT) && images->ft_len)
- theKernel(0, machid, (unsigned long)images->ft_addr);
- else
- theKernel(0, machid, bd->bi_boot_params);
- /* does not return */
-
- return 1;
-}
-
-#ifdef CONFIG_SUPPORT_PASSING_ATAGS
-static void setup_start_tag(struct bd_info *bd)
-{
- params = (struct tag *)bd->bi_boot_params;
-
- params->hdr.tag = ATAG_CORE;
- params->hdr.size = tag_size(tag_core);
-
- params->u.core.flags = 0;
- params->u.core.pagesize = 0;
- params->u.core.rootdev = 0;
-
- params = tag_next(params);
-}
-
-#ifdef CONFIG_SETUP_MEMORY_TAGS
-static void setup_memory_tags(struct bd_info *bd)
-{
- int i;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- params->hdr.tag = ATAG_MEM;
- params->hdr.size = tag_size(tag_mem32);
-
- params->u.mem.start = bd->bi_dram[i].start;
- params->u.mem.size = bd->bi_dram[i].size;
-
- params = tag_next(params);
- }
-}
-#endif /* CONFIG_SETUP_MEMORY_TAGS */
-
-static void setup_commandline_tag(struct bd_info *bd, char *commandline)
-{
- char *p;
-
- if (!commandline)
- return;
-
- /* eat leading white space */
- for (p = commandline; *p == ' '; p++)
- ;
-
- /* skip non-existent command lines so the kernel will still
- * use its default command line.
- */
- if (*p == '\0')
- return;
-
- params->hdr.tag = ATAG_CMDLINE;
- params->hdr.size =
- (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
-
- strcpy(params->u.cmdline.cmdline, p)
- ;
-
- params = tag_next(params);
-}
-
-#ifdef CONFIG_INITRD_TAG
-static void setup_initrd_tag(struct bd_info *bd, ulong initrd_start,
- ulong initrd_end)
-{
- /* an ATAG_INITRD node tells the kernel where the compressed
- * ramdisk can be found. ATAG_RDIMG is a better name, actually.
- */
- params->hdr.tag = ATAG_INITRD2;
- params->hdr.size = tag_size(tag_initrd);
-
- params->u.initrd.start = initrd_start;
- params->u.initrd.size = initrd_end - initrd_start;
-
- params = tag_next(params);
-}
-#endif /* CONFIG_INITRD_TAG */
-
-#ifdef CONFIG_SERIAL_TAG
-void setup_serial_tag(struct tag **tmp)
-{
- struct tag *params = *tmp;
- struct tag_serialnr serialnr;
- void get_board_serial(struct tag_serialnr *serialnr);
-
- get_board_serial(&serialnr);
- params->hdr.tag = ATAG_SERIAL;
- params->hdr.size = tag_size(tag_serialnr);
- params->u.serialnr.low = serialnr.low;
- params->u.serialnr.high = serialnr.high;
- params = tag_next(params);
- *tmp = params;
-}
-#endif
-
-#ifdef CONFIG_REVISION_TAG
-void setup_revision_tag(struct tag **in_params)
-{
- u32 rev = 0;
- u32 get_board_rev(void);
-
- rev = get_board_rev();
- params->hdr.tag = ATAG_REVISION;
- params->hdr.size = tag_size(tag_revision);
- params->u.revision.rev = rev;
- params = tag_next(params);
-}
-#endif /* CONFIG_REVISION_TAG */
-
-static void setup_end_tag(struct bd_info *bd)
-{
- params->hdr.tag = ATAG_NONE;
- params->hdr.size = 0;
-}
-
-#endif /* CONFIG_SUPPORT_PASSING_ATAGS */
-
-static ulong get_sp(void)
-{
- ulong ret;
-
- asm("move %0, $sp" : "=r"(ret) : );
- return ret;
-}
-
-void arch_lmb_reserve(struct lmb *lmb)
-{
- arch_lmb_reserve_generic(lmb, get_sp(), gd->ram_top, 4096);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
-#include <asm/cache.h>
-static inline unsigned long CACHE_SET(unsigned char cache)
-{
- if (cache == ICACHE)
- return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \
- >> ICM_CFG_OFF_ISET);
- else
- return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \
- >> DCM_CFG_OFF_DSET);
-}
-
-static inline unsigned long CACHE_WAY(unsigned char cache)
-{
- if (cache == ICACHE)
- return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \
- >> ICM_CFG_OFF_IWAY);
- else
- return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \
- >> DCM_CFG_OFF_DWAY);
-}
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
- if (cache == ICACHE)
- return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
- >> ICM_CFG_OFF_ISZ) - 1);
- else
- return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
- >> DCM_CFG_OFF_DSZ) - 1);
-}
-#endif
-
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-void invalidate_icache_all(void)
-{
- unsigned long end, line_size;
- line_size = CACHE_LINE_SIZE(ICACHE);
- end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE);
- do {
- end -= line_size;
- __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
-
- end -= line_size;
- __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
-
- end -= line_size;
- __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
- end -= line_size;
- __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end));
- } while (end > 0);
-}
-
-void invalidate_icache_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(ICACHE);
- while (end > start) {
- asm volatile (
- "\n\tcctl %0, L1I_VA_INVAL"
- :
- : "r"(start)
- );
- start += line_size;
- }
-}
-
-void icache_enable(void)
-{
- asm volatile (
- "mfsr $p0, $mr8\n\t"
- "ori $p0, $p0, 0x01\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-void icache_disable(void)
-{
- asm volatile (
- "mfsr $p0, $mr8\n\t"
- "li $p1, ~0x01\n\t"
- "and $p0, $p0, $p1\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-int icache_status(void)
-{
- int ret;
-
- asm volatile (
- "mfsr $p0, $mr8\n\t"
- "andi %0, $p0, 0x01\n\t"
- : "=r" (ret)
- :
- : "memory"
- );
-
- return ret;
-}
-
-#else
-void invalidate_icache_all(void)
-{
-}
-
-void invalidate_icache_range(unsigned long start, unsigned long end)
-{
-}
-
-void icache_enable(void)
-{
-}
-
-void icache_disable(void)
-{
-}
-
-int icache_status(void)
-{
- return 0;
-}
-
-#endif
-
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-void dcache_wbinval_all(void)
-{
- unsigned long end, line_size;
- line_size = CACHE_LINE_SIZE(DCACHE);
- end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE);
- do {
- end -= line_size;
- __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
- __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
- end -= line_size;
- __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
- __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
- end -= line_size;
- __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
- __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
- end -= line_size;
- __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end));
- __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end));
-
- } while (end > 0);
-}
-
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(DCACHE);
-
- while (end > start) {
- asm volatile (
- "\n\tcctl %0, L1D_VA_WB"
- "\n\tcctl %0, L1D_VA_INVAL" : : "r" (start)
- );
- start += line_size;
- }
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(DCACHE);
- while (end > start) {
- asm volatile (
- "\n\tcctl %0, L1D_VA_INVAL" : : "r"(start)
- );
- start += line_size;
- }
-}
-
-void dcache_enable(void)
-{
- asm volatile (
- "mfsr $p0, $mr8\n\t"
- "ori $p0, $p0, 0x02\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-void dcache_disable(void)
-{
- asm volatile (
- "mfsr $p0, $mr8\n\t"
- "li $p1, ~0x02\n\t"
- "and $p0, $p0, $p1\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-int dcache_status(void)
-{
- int ret;
- asm volatile (
- "mfsr $p0, $mr8\n\t"
- "andi %0, $p0, 0x02\n\t"
- : "=r" (ret)
- :
- : "memory"
- );
- return ret;
-}
-
-#else
-void dcache_wbinval_all(void)
-{
-}
-
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
-}
-
-void dcache_enable(void)
-{
-}
-
-void dcache_disable(void)
-{
-}
-
-int dcache_status(void)
-{
- return 0;
-}
-
-#endif
-
-
-void flush_dcache_all(void)
-{
- dcache_wbinval_all();
-}
-
-void cache_flush(void)
-{
- flush_dcache_all();
- invalidate_icache_all();
-}
-
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
- flush_dcache_range(addr, addr + size);
- invalidate_icache_range(addr, addr + size);
-}
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <irq_func.h>
-#include <asm/ptrace.h>
-#include <asm/system.h>
-#undef INTERRUPT_MODE
-
-static int int_flag;
-
-int irq_flags; /* needed by asm-nds32/system.h */
-
-int GIE_STATUS(void)
-{
- int ret;
-
- __asm__ __volatile__ (
- "mfsr $p0, $psw\n\t"
- "andi %0, %0, 0x1\n\t"
- : "=r" (ret)
- :
- : "memory"
- );
- return ret;
-}
-
-#ifdef CONFIG_USE_INTERRUPT
-
-int interrupt_init(void)
-{
- return 0;
-}
-/* enable interrupts */
-void enable_interrupts(void)
-{
- local_irq_restore(int_flag);
-}
-
-/*
- * disable interrupts
- * Return true if GIE is enabled before we disable it.
- */
-int disable_interrupts(void)
-{
-
- int gie_ori_status;
-
- gie_ori_status = GIE_STATUS();
-
- local_irq_save(int_flag);
-
- return gie_ori_status;
-}
-#endif
-
-void bad_mode(void)
-{
- panic("Resetting CPU ...\n");
- reset_cpu();
-}
-
-void show_regs(struct pt_regs *regs)
-{
- const char *processor_modes[] = {"USER", "SuperUser" , "HyperVisor"};
-
- printf("\n");
- printf("pc : [<%08lx>] sp: [<%08lx>]\n"
- "lp : %08lx gp : %08lx fp : %08lx\n",
- regs->ipc, regs->sp, regs->lp, regs->gp, regs->fp);
- printf("D1H: %08lx D1L: %08lx D0H: %08lx D0L: %08lx\n",
- regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
- printf("r27: %08lx r26: %08lx r25: %08lx r24: %08lx\n",
- regs->p1, regs->p0, regs->r[25], regs->r[24]);
- printf("r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n",
- regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
- printf("r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n",
- regs->r[19], regs->r[18], regs->r[17], regs->r[16]);
- printf("r15: %08lx r14: %08lx r13: %08lx r12: %08lx\n",
- regs->r[15], regs->r[14], regs->r[13], regs->r[12]);
- printf("r11: %08lx r10: %08lx r9 : %08lx r8 : %08lx\n",
- regs->r[11], regs->r[10], regs->r[9], regs->r[8]);
- printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
- regs->r[7], regs->r[6], regs->r[5], regs->r[4]);
- printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
- regs->r[3], regs->r[2], regs->r[1], regs->r[0]);
- printf(" Interrupts %s Mode %s\n",
- interrupts_enabled(regs) ? "on" : "off",
- processor_modes[processor_mode(regs)]);
-}
-
-void do_interruption(struct pt_regs *pt_regs, int EVIC_num)
-{
- const char *interruption_type[] = {
- "Reset",
- "TLB Fill",
- "TLB Not Present",
- "TLB Misc",
- "VLPT Miss",
- "Cache Parity Error",
- "Debug",
- "General Exception",
- "External Interrupt"
- };
-
- printf("%s\n", interruption_type[EVIC_num]);
- show_regs(pt_regs);
- bad_mode();
-}
+++ /dev/null
-if TARGET_ADP_AE3XX
-
-config SYS_CPU
- default "n1213"
-
-config SYS_BOARD
- default "adp-ae3xx"
-
-config SYS_VENDOR
- default "AndesTech"
-
-config SYS_SOC
- default "ae3xx"
-
-config SYS_CONFIG_NAME
- default "adp-ae3xx"
-
-endif
+++ /dev/null
-ADP-AG101P BOARD
-M: Andes <uboot@andestech.com>
-S: Maintained
-F: board/AndesTech/adp-ae3xx/
-F: include/configs/adp-ae3xx.h
-F: configs/adp-ae3xx_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2016 Andes Technology Corporation
-# Rick Chen, Andes Technology Corporation <rick@andestech.com>
-
-obj-y := adp-ae3xx.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/mach-types.h>
-#include <common.h>
-#include <flash.h>
-#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
-#include <netdev.h>
-#endif
-#include <linux/io.h>
-#include <faraday/ftsmc020.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initializations
- */
-int board_init(void)
-{
- /*
- * refer to BOOT_PARAMETER_PA_BASE within
- * "linux/arch/nds32/include/asm/misc_spec.h"
- */
- printf("Board: %s\n" , CONFIG_SYS_BOARD);
- gd->bd->bi_arch_number = MACH_TYPE_ADPAE3XX;
- gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
- return 0;
-}
-
-int dram_init(void)
-{
- unsigned long sdram_base = PHYS_SDRAM_0;
- unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
- unsigned long actual_size;
- actual_size = get_ram_size((void *)sdram_base, expected_size);
- gd->ram_size = actual_size;
- if (expected_size != actual_size) {
- printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
- actual_size >> 20, expected_size >> 20);
- }
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
-int board_eth_init(struct bd_info *bd)
-{
- return ftmac100_initialize(bd);
-}
-#endif
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = FLASH_CFI_8BIT;
- info->chipwidth = FLASH_CFI_BY8;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else {
- return 0;
- }
-}
+++ /dev/null
-if TARGET_ADP_AG101P
-
-config DEBUG_LED
- hex
- default 0x902FFFFC
-
-config SYS_CPU
- default "n1213"
-
-config SYS_BOARD
- default "adp-ag101p"
-
-config SYS_VENDOR
- default "AndesTech"
-
-config SYS_SOC
- default "ag101"
-
-config SYS_CONFIG_NAME
- default "adp-ag101p"
-
-endif
+++ /dev/null
-ADP-AG101P BOARD
-M: Andes <uboot@andestech.com>
-S: Maintained
-F: board/AndesTech/adp-ag101p/
-F: include/configs/adp-ag101p.h
-F: configs/adp-ag101p_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Andes Technology Corporation
-# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
-# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
-
-obj-y := adp-ag101p.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#include <common.h>
-#include <flash.h>
-#include <init.h>
-#include <net.h>
-#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
-#include <netdev.h>
-#endif
-#include <asm/global_data.h>
-#include <linux/io.h>
-#include <asm/io.h>
-#include <asm/mach-types.h>
-
-#include <faraday/ftsmc020.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Miscellaneous platform dependent initializations
- */
-
-int board_init(void)
-{
- /*
- * refer to BOOT_PARAMETER_PA_BASE within
- * "linux/arch/nds32/include/asm/misc_spec.h"
- */
- printf("Board: %s\n" , CONFIG_SYS_BOARD);
- gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
- gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
-
- return 0;
-}
-
-int dram_init(void)
-{
- unsigned long sdram_base = PHYS_SDRAM_0;
- unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
- unsigned long actual_size;
-
- actual_size = get_ram_size((void *)sdram_base, expected_size);
-
- gd->ram_size = actual_size;
-
- if (expected_size != actual_size) {
- printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
- actual_size >> 20, expected_size >> 20);
- }
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_0_SIZE;
- gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[1].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
-int board_eth_init(struct bd_info *bd)
-{
- return ftmac100_initialize(bd);
-}
-#endif
-
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
-{
- if (banknum == 0) { /* non-CFI boot flash */
- info->portwidth = FLASH_CFI_8BIT;
- info->chipwidth = FLASH_CFI_BY8;
- info->interface = FLASH_CFI_X8;
- return 1;
- } else {
- return 0;
- }
-}
gd->mon_len = (ulong)&_end - (ulong)_init;
#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
-#elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
+#elif defined(CONFIG_SH) || defined(CONFIG_RISCV)
gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
#elif defined(CONFIG_SYS_MONITOR_BASE)
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
{
#ifdef __ARM__
monitor_flash_len = _end - __image_copy_start;
-#elif defined(CONFIG_NDS32) || defined(CONFIG_RISCV)
+#elif defined(CONFIG_RISCV)
monitor_flash_len = (ulong)&_end - (ulong)&_start;
#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
#ifdef CONFIG_ADDR_MAP
init_addr_map,
#endif
-#if defined(CONFIG_ARM) || defined(CONFIG_NDS32) || defined(CONFIG_RISCV) || \
- defined(CONFIG_SANDBOX)
+#if defined(CONFIG_ARM) || defined(CONFIG_RISCV) || defined(CONFIG_SANDBOX)
board_init, /* Setup chipselects */
#endif
/*
+++ /dev/null
-CONFIG_NDS32=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_SYS_TEXT_BASE=0x4A000000
-CONFIG_SYS_MALLOC_LEN=0x80000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0x140000
-CONFIG_ENV_SECT_SIZE=0x1000
-CONFIG_DEFAULT_DEVICE_TREE="ae3xx"
-CONFIG_SYS_CLK_FREQ=39062500
-CONFIG_SYS_LOAD_ADDR=0x300000
-CONFIG_TARGET_ADP_AE3XX=y
-CONFIG_FIT=y
-CONFIG_SYS_MONITOR_BASE=0x88000000
-CONFIG_BOOTDELAY=3
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="NDS32 # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF_TEST=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_BOOTP_SERVERIP=y
-CONFIG_DM=y
-CONFIG_CLK=y
-CONFIG_MMC=y
-CONFIG_FTSDC010=y
-CONFIG_FTSDC010_SDIO=y
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_CFI_FLASH=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_DM_ETH=y
-CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_ATCSPI200_SPI=y
-CONFIG_TIMER=y
-CONFIG_ATCPIT100_TIMER=y
-CONFIG_PANIC_HANG=y
+++ /dev/null
-CONFIG_NDS32=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_SYS_TEXT_BASE=0x11000000
-CONFIG_SYS_MALLOC_LEN=0x80000
-CONFIG_SYS_MALLOC_F_LEN=0x400
-CONFIG_NR_DRAM_BANKS=2
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_DEFAULT_DEVICE_TREE="ag101p"
-CONFIG_SYS_CLK_FREQ=39062500
-CONFIG_SYS_LOAD_ADDR=0x300000
-CONFIG_ENV_ADDR=0x80140000
-CONFIG_TARGET_ADP_AG101P=y
-CONFIG_FIT=y
-CONFIG_SYS_MONITOR_BASE=0x80000000
-CONFIG_BOOTDELAY=3
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="NDS32 # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_MMC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_DATE=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_OF_CONTROL=y
-CONFIG_OF_EMBED=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_BOOTP_SERVERIP=y
-CONFIG_DM=y
-CONFIG_MMC=y
-CONFIG_FTSDC010=y
-CONFIG_FTSDC010_SDIO=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_DM_ETH=y
-CONFIG_FTMAC100=y
-CONFIG_BAUDRATE=38400
-CONFIG_DM_SERIAL=y
-CONFIG_SYS_NS16550=y
-CONFIG_TIMER=y
-CONFIG_AG101P_TIMER=y
ARM 0x0c100000 0x0c100000
MIPS 0x80200000 0x80200000
Blackfin 0x00001000 0x00001000
- NDS32 0x00300000 0x00300000
Nios II 0x02000000 0x02000000
RISC-V 0x00600000 0x00600000
CONFIG_WDT_AT91
Available for AT91SAM9 to service the watchdog.
-CONFIG_FTWDT010_WATCHDOG
- Available for FTWDT010 to service the watchdog.
-
-CONFIG_FTWDT010_HW_TIMEOUT
- Can be used to change the timeout for FTWDT010.
-
CONFIG_IMX_WATCHDOG
Available for i.mx31/35/5x/6x to service the watchdog. This is not
automatically set because some boards (vision2) still need to define
arm64
m68k
mips
- nds32
nios2
sandbox
sh
+++ /dev/null
-.. SPDX-License-Identifier: GPL-2.0+
-
-NDS32
-=====
-
-NDS32 is a new high-performance 32-bit RISC microprocessor core.
-
-http://www.andestech.com/
-
-AndeStar ISA
-------------
-AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
-achieve optimal system performance, code density, and power efficiency.
-
-It contains the following features:
- - Intermixable 32-bit and 16-bit instruction sets without the need for
- mode switch.
- - 16-bit instructions as a frequently used subset of 32-bit instructions.
- - RISC-style register-based instruction set.
- - 32 32-bit General Purpose Registers (GPR).
- - Upto 1024 User Special Registers (USR) for existing and extension
- instructions.
- - Rich load/store instructions for...
- - Single memory access with base address update.
- - Multiple aligned and unaligned memory accesses for memory copy and stack
- operations.
- - Data prefetch to improve data cache performance.
- - Non-bus locking synchronization instructions.
- - PC relative jump and PC read instructions for efficient position independent
- code.
- - Multiply-add and multiple-sub with 64-bit accumulator.
- - Instruction for efficient power management.
- - Bi-endian support.
- - Three instruction extension space for application acceleration:
- - Performance extension.
- - Andes future extensions (for floating-point, multimedia, etc.)
- - Customer extensions.
-
-AndesCore CPU
--------------
-Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
-
-For details about N12 CPU family, please check below N1213 features.
-N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
-
-N1213 Features
-^^^^^^^^^^^^^^
-
-CPU Core
- - 16-/32-bit mixable instruction format.
- - 32 general-purpose 32-bit registers.
- - 8-stage pipeline.
- - Dynamic branch prediction.
- - 32/64/128/256 BTB.
- - Return address stack (RAS).
- - Vector interrupts for internal/external.
- interrupt controller with 6 hardware interrupt signals.
- - 3 HW-level nested interruptions.
- - User and super-user mode support.
- - Memory-mapped I/O.
- - Address space up to 4GB.
-
-Memory Management Unit
- - TLB
- - 4/8-entry fully associative iTLB/dTLB.
- - 32/64/128-entry 4-way set-associati.ve main TLB.
- - TLB locking support
- - Optional hardware page table walker.
- - Two groups of page size support.
- - 4KB & 1MB.
- - 8KB & 1MB.
-
-Memory Subsystem
- - I & D cache.
- - Virtually indexed and physically tagged.
- - Cache size: 8KB/16KB/32KB/64KB.
- - Cache line size: 16B/32B.
- - Set associativity: 2-way, 4-way or direct-mapped.
- - Cache locking support.
- - I & D local memory (LM).
- - Size: 4KB to 1MB.
- - Bank numbers: 1 or 2.
- - Optional 1D/2D DMA engine.
- - Internal or external to CPU core.
-
-Bus Interface
- - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
- - Synchronous High speed memory port.
- (HSMP): 0, 1 or 2 ports.
-
-Debug
- - JTAG debug interface.
- - Embedded debug module (EDM).
- - Optional embedded program tracer interface.
-
-Miscellaneous
- - Programmable data endian control.
- - Performance monitoring mechanism.
-
-The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and other
-associated software are actively supported by Andes Technology Corporation.
+------------+----------+
| MicroBlaze | r31 |
+------------+----------+
-| NDS32 | r10 |
-+------------+----------+
| Nios II | gp |
+------------+----------+
| PowerPC | r2 |
alias priyankajain Priyanka Jain <priyanka.jain@nxp.com>
# Architecture aliases
-alias arch arc, arm, m68k, microblaze, mips, nds32, nios2, powerpc, sandbox, superh, x86
+alias arch arc, arm, m68k, microblaze, mips, nios2, powerpc, sandbox, superh, x86
alias arches arch
alias arc uboot, abrodkin
alias mips uboot, danielschwierzeck
-alias nds32 uboot, macpaul
-
alias nios uboot, Thomas Chou <thomas@wytron.com.tw>, smcnutt
alias nios2 nios
use an early timer. These functions must be supported by your timer
driver: timer_early_get_count() and timer_early_get_rate().
-config AG101P_TIMER
- bool "AG101P timer support"
- depends on TIMER && NDS32
- help
- Select this to enable a timer for AG01P devices.
-
config ALTERA_TIMER
bool "Altera timer support"
depends on TIMER
# Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
obj-y += timer-uclass.o
-obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AST_TIMER) += ast_timer.o
-obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
obj-$(CONFIG_ATMEL_TCB_TIMER) += atmel_tcb_timer.o
obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Andestech ATFTMR010 timer driver
- *
- * (C) Copyright 2016
- * Rick Chen, NDS32 Software Engineering, rick@andestech.com
- */
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <timer.h>
-#include <linux/io.h>
-
-/*
- * Timer Control Register
- */
-#define T3_UPDOWN (1 << 11)
-#define T2_UPDOWN (1 << 10)
-#define T1_UPDOWN (1 << 9)
-#define T3_OFENABLE (1 << 8)
-#define T3_CLOCK (1 << 7)
-#define T3_ENABLE (1 << 6)
-#define T2_OFENABLE (1 << 5)
-#define T2_CLOCK (1 << 4)
-#define T2_ENABLE (1 << 3)
-#define T1_OFENABLE (1 << 2)
-#define T1_CLOCK (1 << 1)
-#define T1_ENABLE (1 << 0)
-
-/*
- * Timer Interrupt State & Mask Registers
- */
-#define T3_OVERFLOW (1 << 8)
-#define T3_MATCH2 (1 << 7)
-#define T3_MATCH1 (1 << 6)
-#define T2_OVERFLOW (1 << 5)
-#define T2_MATCH2 (1 << 4)
-#define T2_MATCH1 (1 << 3)
-#define T1_OVERFLOW (1 << 2)
-#define T1_MATCH2 (1 << 1)
-#define T1_MATCH1 (1 << 0)
-
-struct atftmr_timer_regs {
- u32 t1_counter; /* 0x00 */
- u32 t1_load; /* 0x04 */
- u32 t1_match1; /* 0x08 */
- u32 t1_match2; /* 0x0c */
- u32 t2_counter; /* 0x10 */
- u32 t2_load; /* 0x14 */
- u32 t2_match1; /* 0x18 */
- u32 t2_match2; /* 0x1c */
- u32 t3_counter; /* 0x20 */
- u32 t3_load; /* 0x24 */
- u32 t3_match1; /* 0x28 */
- u32 t3_match2; /* 0x2c */
- u32 cr; /* 0x30 */
- u32 int_state; /* 0x34 */
- u32 int_mask; /* 0x38 */
-};
-
-struct atftmr_timer_plat {
- struct atftmr_timer_regs *regs;
-};
-
-static u64 atftmr_timer_get_count(struct udevice *dev)
-{
- struct atftmr_timer_plat *plat = dev_get_plat(dev);
- struct atftmr_timer_regs *const regs = plat->regs;
- u32 val;
- val = readl(®s->t3_counter);
- return timer_conv_64(val);
-}
-
-static int atftmr_timer_probe(struct udevice *dev)
-{
- struct atftmr_timer_plat *plat = dev_get_plat(dev);
- struct atftmr_timer_regs *const regs = plat->regs;
- u32 cr;
- writel(0, ®s->t3_load);
- writel(0, ®s->t3_counter);
- writel(TIMER_LOAD_VAL, ®s->t3_match1);
- writel(TIMER_LOAD_VAL, ®s->t3_match2);
- /* disable interrupts */
- writel(T3_MATCH1|T3_MATCH2|T3_OVERFLOW , ®s->int_mask);
- cr = readl(®s->cr);
- cr |= (T3_ENABLE|T3_UPDOWN);
- writel(cr, ®s->cr);
- return 0;
-}
-
-static int atftme_timer_of_to_plat(struct udevice *dev)
-{
- struct atftmr_timer_plat *plat = dev_get_plat(dev);
- plat->regs = map_physmem(dev_read_addr(dev),
- sizeof(struct atftmr_timer_regs),
- MAP_NOCACHE);
- return 0;
-}
-
-static const struct timer_ops ag101p_timer_ops = {
- .get_count = atftmr_timer_get_count,
-};
-
-static const struct udevice_id ag101p_timer_ids[] = {
- { .compatible = "andestech,attmr010" },
- {}
-};
-
-U_BOOT_DRIVER(altera_timer) = {
- .name = "ag101p_timer",
- .id = UCLASS_TIMER,
- .of_match = ag101p_timer_ids,
- .of_to_plat = atftme_timer_of_to_plat,
- .plat_auto = sizeof(struct atftmr_timer_plat),
- .probe = atftmr_timer_probe,
- .ops = &ag101p_timer_ops,
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Andestech ATCPIT100 timer driver
- *
- * (C) Copyright 2016
- * Rick Chen, NDS32 Software Engineering, rick@andestech.com
- */
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <timer.h>
-#include <linux/io.h>
-
-#define REG32_TMR(x) (*(u32 *) ((plat->regs) + (x>>2)))
-
-/*
- * Definition of register offsets
- */
-
-/* ID and Revision Register */
-#define ID_REV 0x0
-
-/* Configuration Register */
-#define CFG 0x10
-
-/* Interrupt Enable Register */
-#define INT_EN 0x14
-#define CH_INT_EN(c , i) ((1<<i)<<(4*c))
-
-/* Interrupt Status Register */
-#define INT_STA 0x18
-#define CH_INT_STA(c , i) ((1<<i)<<(4*c))
-
-/* Channel Enable Register */
-#define CH_EN 0x1C
-#define CH_TMR_EN(c , t) ((1<<t)<<(4*c))
-
-/* Ch n Control REgister */
-#define CH_CTL(n) (0x20+0x10*n)
-/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
-#define APB_CLK (1<<3)
-/* Channel mode , bit 0~2 */
-#define TMR_32 1
-#define TMR_16 2
-#define TMR_8 3
-#define PWM 4
-
-#define CH_REL(n) (0x24+0x10*n)
-#define CH_CNT(n) (0x28+0x10*n)
-
-struct atctmr_timer_regs {
- u32 id_rev; /* 0x00 */
- u32 reservd[3]; /* 0x04 ~ 0x0c */
- u32 cfg; /* 0x10 */
- u32 int_en; /* 0x14 */
- u32 int_st; /* 0x18 */
- u32 ch_en; /* 0x1c */
- u32 ch0_ctrl; /* 0x20 */
- u32 ch0_reload; /* 0x24 */
- u32 ch0_cntr; /* 0x28 */
- u32 reservd1; /* 0x2c */
- u32 ch1_ctrl; /* 0x30 */
- u32 ch1_reload; /* 0x34 */
- u32 int_mask; /* 0x38 */
-};
-
-struct atcpit_timer_plat {
- u32 *regs;
-};
-
-static u64 atcpit_timer_get_count(struct udevice *dev)
-{
- struct atcpit_timer_plat *plat = dev_get_plat(dev);
- u32 val;
- val = ~(REG32_TMR(CH_CNT(1))+0xffffffff);
- return timer_conv_64(val);
-}
-
-static int atcpit_timer_probe(struct udevice *dev)
-{
- struct atcpit_timer_plat *plat = dev_get_plat(dev);
- REG32_TMR(CH_REL(1)) = 0xffffffff;
- REG32_TMR(CH_CTL(1)) = APB_CLK|TMR_32;
- REG32_TMR(CH_EN) |= CH_TMR_EN(1 , 0);
- return 0;
-}
-
-static int atcpit_timer_of_to_plat(struct udevice *dev)
-{
- struct atcpit_timer_plat *plat = dev_get_plat(dev);
- plat->regs = map_physmem(dev_read_addr(dev), 0x100 , MAP_NOCACHE);
- return 0;
-}
-
-static const struct timer_ops atcpit_timer_ops = {
- .get_count = atcpit_timer_get_count,
-};
-
-static const struct udevice_id atcpit_timer_ids[] = {
- { .compatible = "andestech,atcpit100" },
- {}
-};
-
-U_BOOT_DRIVER(atcpit100_timer) = {
- .name = "atcpit100_timer",
- .id = UCLASS_TIMER,
- .of_match = atcpit_timer_ids,
- .of_to_plat = atcpit_timer_of_to_plat,
- .plat_auto = sizeof(struct atcpit_timer_plat),
- .probe = atcpit_timer_probe,
- .ops = &atcpit_timer_ops,
-};
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-$(CONFIG_WDT_AT91) += at91sam9_wdt.o
-obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 vf610))
obj-y += imx_watchdog.o
else
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Watchdog driver for the FTWDT010 Watch Dog Driver
- *
- * (c) Copyright 2004 Faraday Technology Corp. (www.faraday-tech.com)
- * Based on sa1100_wdt.c by Oleg Drokin <green@crimea.edu>
- * Based on SoftDog driver by Alan Cox <alan@redhat.com>
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- *
- * 27/11/2004 Initial release, Faraday.
- * 12/01/2011 Port to u-boot, Macpaul Lin.
- */
-
-#include <common.h>
-#include <log.h>
-#include <watchdog.h>
-#include <asm/io.h>
-#include <faraday/ftwdt010_wdt.h>
-
-/*
- * Set the watchdog time interval.
- * Counter is 32 bit.
- */
-int ftwdt010_wdt_settimeout(unsigned int timeout)
-{
- unsigned int reg;
-
- struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE;
-
- debug("Activating WDT..\n");
-
- /* Check if disabled */
- if (readl(&wd->wdcr) & ~FTWDT010_WDCR_ENABLE) {
- printf("sorry, watchdog is disabled\n");
- return -1;
- }
-
- /*
- * In a 66MHz system,
- * if you set WDLOAD as 0x03EF1480 (66000000)
- * the reset timer is 1 second.
- */
- reg = FTWDT010_WDLOAD(timeout * FTWDT010_TIMEOUT_FACTOR);
-
- writel(reg, &wd->wdload);
-
- return 0;
-}
-
-void ftwdt010_wdt_reset(void)
-{
- struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE;
-
- /* clear control register */
- writel(0, &wd->wdcr);
-
- /* Write Magic number */
- writel(FTWDT010_WDRESTART_MAGIC, &wd->wdrestart);
-
- /* Enable WDT */
- writel((FTWDT010_WDCR_RST | FTWDT010_WDCR_ENABLE), &wd->wdcr);
-}
-
-void ftwdt010_wdt_disable(void)
-{
- struct ftwdt010_wdt *wd = (struct ftwdt010_wdt *)CONFIG_FTWDT010_BASE;
-
- debug("Deactivating WDT..\n");
-
- /*
- * It was defined with CONFIG_WATCHDOG_NOWAYOUT in Linux
- *
- * Shut off the timer.
- * Lock it in if it's a module and we defined ...NOWAYOUT
- */
- writel(0, &wd->wdcr);
-}
-
-#if defined(CONFIG_HW_WATCHDOG)
-void hw_watchdog_reset(void)
-{
- ftwdt010_wdt_reset();
-}
-
-void hw_watchdog_init(void)
-{
- /* set timer in ms */
- ftwdt010_wdt_settimeout(CONFIG_FTWDT010_HW_TIMEOUT * 1000);
-}
-#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-OUTPUT_FORMAT("elf32-nds32", "elf32-nds32", "elf32-nds32")
-OUTPUT_ARCH(nds32)
-ENTRY(_start)
-SECTIONS
-{
- . = ALIGN(4);
- .text :
- {
- *(.text)
- }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
-
- .got : {
- __got_start = .;
- *(.got)
- __got_end = .;
- }
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- __bss_end = .;
-
- . = ALIGN(4);
- .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
-
- _end = .;
-}
" nop\n" \
" nop\n" \
: : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "r1", "r2");
-#elif defined(CONFIG_NDS32)
-/*
- * r16 holds the pointer to the global_data. gp is call clobbered.
- * not support reduced register (16 GPR).
- */
-#define EXPORT_FUNC(f, a, x, ...) \
- asm volatile ( \
-" .globl " #x "\n" \
-#x ":\n" \
-" lwi $r16, [$gp + (%0)]\n" \
-" lwi $r16, [$r16 + (%1)]\n" \
-" jr $r16\n" \
- : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "$r16");
#elif defined(CONFIG_RISCV)
/*
* gp holds the pointer to the global_data. t0 is call clobbered.
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch-ae3xx/ae3xx.h>
-
-/*
- * CPU and Board Configuration Options
- */
-#define CONFIG_USE_INTERRUPT
-
-#define CONFIG_SKIP_TRUNOFF_WATCHDOG
-
-/*
- * Timer
- */
-#define VERSION_CLOCK get_board_sys_clk()
-
-/*
- * Use Externel CLOCK or PCLK
- */
-#undef CONFIG_FTRTC010_EXTCLK
-
-#ifndef CONFIG_FTRTC010_EXTCLK
-#define CONFIG_FTRTC010_PCLK
-#endif
-
-#ifdef CONFIG_FTRTC010_EXTCLK
-#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
-#else
-#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
-#endif
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-/*
- * Real Time Clock
- */
-#define CONFIG_RTC_FTRTC010
-
-/*
- * Real Time Clock Divider
- * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
- */
-#define OSC_5MHZ (5*1000000)
-#define OSC_CLK (4*OSC_5MHZ)
-#define RTC_DIV_COUNT (0.5) /* Why?? */
-
-/*
- * Serial console configuration
- */
-
-/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#endif
-#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * Size of malloc() pool
- */
-/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
-
-/*
- * Physical Memory Map
- */
-#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
-
-#define PHYS_SDRAM_1 \
- (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
-
-#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
- GENERATED_GBL_DATA_SIZE)
-
-/*
- * Static memory controller configuration
- */
-#define CONFIG_FTSMC020
-
-#ifdef CONFIG_FTSMC020
-#include <faraday/ftsmc020.h>
-
-#define CONFIG_SYS_FTSMC020_CONFIGS { \
- { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
- { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
-}
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
-#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
- FTSMC020_BANK_SIZE_32M | \
- FTSMC020_BANK_MBW_32)
-
-#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
- FTSMC020_TPR_AST(1) | \
- FTSMC020_TPR_CTW(1) | \
- FTSMC020_TPR_ATI(1) | \
- FTSMC020_TPR_AT2(1) | \
- FTSMC020_TPR_WTC(1) | \
- FTSMC020_TPR_AHT(1) | \
- FTSMC020_TPR_TRNA(1))
-#endif
-
-/*
- * FLASH on ADP_AG101P is connected to BANK0
- * Just disalbe the other BANK to avoid detection error.
- */
-#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
- FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
- FTSMC020_BANK_SIZE_32M | \
- FTSMC020_BANK_MBW_32)
-
-#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
- FTSMC020_TPR_CTW(3) | \
- FTSMC020_TPR_ATI(0xf) | \
- FTSMC020_TPR_AT2(3) | \
- FTSMC020_TPR_WTC(3) | \
- FTSMC020_TPR_AHT(3) | \
- FTSMC020_TPR_TRNA(0xf))
-
-#define FTSMC020_BANK1_CONFIG (0x00)
-#define FTSMC020_BANK1_TIMING (0x00)
-#endif /* CONFIG_FTSMC020 */
-
-/*
- * FLASH and environment organization
- */
-/* use CFI framework */
-
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
-
-/* support JEDEC */
-
-/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
-#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
-
-/* max number of memory banks */
-/*
- * There are 4 banks supported for this Controller,
- * but we have only 1 bank connected to flash on board
- */
-#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
-
-/* max number of sectors on one chip */
-#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-/* environments */
-
-
-/* SPI FLASH */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-
-/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
-/* Increase max gunzip size */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Andes Technology Corporation
- * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch-ag101/ag101.h>
-
-/*
- * CPU and Board Configuration Options
- */
-#define CONFIG_USE_INTERRUPT
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_MEM_REMAP
-#endif
-
-/*
- * Timer
- */
-#define VERSION_CLOCK get_board_sys_clk()
-
-/*
- * Use Externel CLOCK or PCLK
- */
-#undef CONFIG_FTRTC010_EXTCLK
-
-#ifndef CONFIG_FTRTC010_EXTCLK
-#define CONFIG_FTRTC010_PCLK
-#endif
-
-#ifdef CONFIG_FTRTC010_EXTCLK
-#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
-#else
-#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
-#endif
-
-#define TIMER_LOAD_VAL 0xffffffff
-
-/*
- * Real Time Clock
- */
-#define CONFIG_RTC_FTRTC010
-
-/*
- * Real Time Clock Divider
- * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
- */
-#define OSC_5MHZ (5*1000000)
-#define OSC_CLK (4*OSC_5MHZ)
-#define RTC_DIV_COUNT (0.5) /* Why?? */
-
-/*
- * Serial console configuration
- */
-
-/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
-#ifndef CONFIG_DM_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#endif
-#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
-
-/*
- * Miscellaneous configurable options
- */
-
-/*
- * AHB Controller configuration
- */
-#define CONFIG_FTAHBC020S
-
-#ifdef CONFIG_FTAHBC020S
-#include <faraday/ftahbc020s.h>
-
-/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
-#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
-
-/*
- * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
- * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
- * in C language.
- */
-#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
- (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
- FTAHBC020S_SLAVE_BSR_SIZE(0xb))
-#endif
-
-/*
- * Watchdog
- */
-#define CONFIG_FTWDT010_WATCHDOG
-
-/*
- * PMU Power controller configuration
- */
-#define CONFIG_PMU
-#define CONFIG_FTPMU010_POWER
-
-#ifdef CONFIG_FTPMU010_POWER
-#include <faraday/ftpmu010.h>
-#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
-#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
- FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
- FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
- FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
- FTPMU010_SDRAMHTC_CKE_DCSR | \
- FTPMU010_SDRAMHTC_DQM_DCSR | \
- FTPMU010_SDRAMHTC_SDCLK_DCSR)
-#endif
-
-/*
- * SDRAM controller configuration
- */
-#define CONFIG_FTSDMC021
-
-#ifdef CONFIG_FTSDMC021
-#include <faraday/ftsdmc021.h>
-
-#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
- FTSDMC021_TP1_TRP(1) | \
- FTSDMC021_TP1_TRCD(1) | \
- FTSDMC021_TP1_TRF(3) | \
- FTSDMC021_TP1_TWR(1) | \
- FTSDMC021_TP1_TCL(2))
-
-#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
- FTSDMC021_TP2_INI_REFT(8) | \
- FTSDMC021_TP2_REF_INTV(0x180))
-
-/*
- * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
- * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
- * C language.
- */
-#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
- FTSDMC021_CR1_DSZ(3) | \
- FTSDMC021_CR1_MBW(2) | \
- FTSDMC021_CR1_BNKSIZE(6))
-
-#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
- FTSDMC021_CR2_IREF | \
- FTSDMC021_CR2_ISMR)
-
-#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
-#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
- CONFIG_SYS_FTSDMC021_BANK0_BASE)
-
-#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
- (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
-#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
- CONFIG_SYS_FTSDMC021_BANK1_BASE)
-#endif
-
-/*
- * Physical Memory Map
- */
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
-#else
-#ifdef CONFIG_MEM_REMAP
-#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
-#else
-#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
-#endif
-#endif
-
-#define PHYS_SDRAM_1 \
- (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
-
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
-#else
-#ifdef CONFIG_MEM_REMAP
-#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
-#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
-#else
-#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#endif
-#endif
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
-
-#ifdef CONFIG_MEM_REMAP
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
- GENERATED_GBL_DATA_SIZE)
-#else
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
- GENERATED_GBL_DATA_SIZE)
-#endif /* CONFIG_MEM_REMAP */
-
-/*
- * Static memory controller configuration
- */
-#define CONFIG_FTSMC020
-
-#ifdef CONFIG_FTSMC020
-#include <faraday/ftsmc020.h>
-
-#define CONFIG_SYS_FTSMC020_CONFIGS { \
- { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
- { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
-}
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
-#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
- FTSMC020_BANK_SIZE_32M | \
- FTSMC020_BANK_MBW_32)
-
-#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
- FTSMC020_TPR_AST(1) | \
- FTSMC020_TPR_CTW(1) | \
- FTSMC020_TPR_ATI(1) | \
- FTSMC020_TPR_AT2(1) | \
- FTSMC020_TPR_WTC(1) | \
- FTSMC020_TPR_AHT(1) | \
- FTSMC020_TPR_TRNA(1))
-#endif
-
-/*
- * FLASH on ADP_AG101P is connected to BANK0
- * Just disalbe the other BANK to avoid detection error.
- */
-#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
- FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
- FTSMC020_BANK_SIZE_32M | \
- FTSMC020_BANK_MBW_32)
-
-#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
- FTSMC020_TPR_CTW(3) | \
- FTSMC020_TPR_ATI(0xf) | \
- FTSMC020_TPR_AT2(3) | \
- FTSMC020_TPR_WTC(3) | \
- FTSMC020_TPR_AHT(3) | \
- FTSMC020_TPR_TRNA(0xf))
-
-#define FTSMC020_BANK1_CONFIG (0x00)
-#define FTSMC020_BANK1_TIMING (0x00)
-#endif /* CONFIG_FTSMC020 */
-
-/*
- * FLASH and environment organization
- */
-/* use CFI framework */
-
-#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
-
-/* support JEDEC */
-
-/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
-#ifdef CONFIG_SKIP_LOWLEVEL_INIT
-#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
-#else
-#ifdef CONFIG_MEM_REMAP
-#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
-#else
-#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
-#endif
-#endif /* CONFIG_MEM_REMAP */
-
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
-
-/* max number of memory banks */
-/*
- * There are 4 banks supported for this Controller,
- * but we have only 1 bank connected to flash on board
- */
-#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
-
-/* max number of sectors on one chip */
-#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-/* environments */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 16 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-
-/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
-/* Increase max gunzip size */
-#define CONFIG_SYS_BOOTM_LEN (64 << 20)
-
-#endif /* __CONFIG_H */
config LMB
bool "Enable the logical memory blocks library (lmb)"
- default y if ARC || ARM || M68K || MICROBLAZE || MIPS || NDS32 || \
+ default y if ARC || ARM || M68K || MICROBLAZE || MIPS || \
NIOS2 || PPC || RISCV || SANDBOX || SH || X86 || XTENSA
help
Support the library logical memory blocks.
barnum = (barnum - PCI_BASE_ADDRESS_0) / 4;
- /*
- * There is a strange toolchain bug with nds32 which complains about
- * an undefined reference here, even if fdtdec_get_pci_bar32() is never
- * called. An #ifdef seems to be the only fix!
- */
-#if !IS_ENABLED(CONFIG_NDS32)
*bar = dm_pci_read_bar32(dev, barnum);
-#endif
return 0;
}
[toolchain-alias]
x86: i386
blackfin: bfin
-nds32: nds32le
openrisc: or1k
download/arc-2016.09-release/arc_gnu_2016.09_prebuilt_uclibc_le_archs_linux_install.tar.gz
blackfin: http://sourceforge.net/projects/adi-toolchain/files/
blackfin-toolchain-elf-gcc-4.5-2014R1_45-RC2.x86_64.tar.bz2
-nds32: http://osdk.andestech.com/packages/
- nds32le-linux-glibc-v1.tgz
nios2: http://sourcery.mentor.com/public/gnu_toolchain/nios2-linux-gnu/
sourceryg++-2015.11-27-nios2-linux-gnu-i686-pc-linux-gnu.tar.bz2
sh: http://sourcery.mentor.com/public/gnu_toolchain/sh-linux-gnu/
At the time of writing, U-Boot has these architectures:
- arc, arm, blackfin, m68k, microblaze, mips, nds32, nios2, openrisc
+ arc, arm, blackfin, m68k, microblaze, mips, nios2, openrisc
powerpc, sandbox, sh, sparc, x86
-Of these, only arc and nds32 are not available at kernel.org..
+Of these, only arc is not available at kernel.org..
How to run it
# Indicates which toolchain should be used to build for that arch
x86 = i386
blackfin = bfin
-nds32 = nds32le
openrisc = or1k
[make-flags]
For example:
powerpc: (622 boards) text -0.0
arm: (285 boards) text -0.0
- nds32: (3 boards) text -8.0
Args:
board_selected: Dict containing boards to summarise, keyed by
# Manually install other toolchains
RUN wget -O - https://github.com/foss-xtensa/toolchain/releases/download/2020.07/x86_64-2020.07-xtensa-dc233c-elf.tar.gz | tar -C /opt -xz
RUN wget -O - https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2021.03-release/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install.tar.gz | tar --no-same-owner -C /opt -xz
-RUN wget -O - https://github.com/vincentzwc/prebuilt-nds32-toolchain/releases/download/20180521/nds32le-linux-glibc-v3-upstream.tar.gz | tar -C /opt -xz
# Update and install things from apt now
RUN apt-get update && apt-get install -y \
RUN /bin/echo -e "kernelorg = /opt/gcc-11.1.0-nolibc/*" >> ~/.buildman
RUN /bin/echo -e "arc = /opt/arc_gnu_2021.03_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
RUN /bin/echo -e "\n[toolchain-prefix]\nxtensa = /opt/2020.07/xtensa-dc233c-elf/bin/xtensa-dc233c-elf-" >> ~/.buildman;
-RUN /bin/echo -e "\nnds32 = /opt/nds32le-linux-glibc-v3-upstream/bin/nds32le-linux-" >> ~/.buildman;
RUN /bin/echo -e "\n[toolchain-alias]\nsh = sh2" >> ~/.buildman
RUN /bin/echo -e "\nriscv = riscv64" >> ~/.buildman
RUN /bin/echo -e "\nsandbox = x86_64" >> ~/.buildman
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