arm: actions: add S700 SoC device tree

This patch adds .dtsi file(sync with Linux 5.5-rc6 with hash "b3a987b0264d")
and required binding for S700 SoC that is a 64-bit Quad-core ARM
Cortex-A53 cores.

It also provisions dts file to be built based on selected
platform(CONFIG_MACH_S900/S700).

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ba96efaa1e6ccd8b0b0bcf026753d28d5231612c..af7d804b6669bcb0e9ab0ce79a02a1bf94226031 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -66,6 +66,8 @@ dtb-$(CONFIG_KIRKWOOD) += \
 
 dtb-$(CONFIG_MACH_S900) += \
        bubblegum_96.dtb
+dtb-$(CONFIG_MACH_S700) += \
+       s700-cubieboard7.dtb
 
 dtb-$(CONFIG_ROCKCHIP_PX30) += \
        px30-evb.dtb \

diff --git a/arch/arm/dts/s700.dtsi b/arch/arm/dts/s700.dtsi
new file mode 100644 (file)
index 0000000..2006ad5
--- /dev/null
+++ b/arch/arm/dts/s700.dtsi
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Andreas Färber
+ */
+
+#include <dt-bindings/clock/actions,s700-cmu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/actions,s700-reset.h>
+
+/ {
+       compatible = "actions,s700";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x0>;
+                       enable-method = "psci";
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x1>;
+                       enable-method = "psci";
+               };
+
+               cpu2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x2>;
+                       enable-method = "psci";
+               };
+
+               cpu3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53";
+                       reg = <0x0 0x3>;
+                       enable-method = "psci";
+               };
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               secmon@1f000000 {
+                       reg = <0x0 0x1f000000 0x0 0x1000000>;
+                       no-map;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       arm-pmu {
+               compatible = "arm,cortex-a53-pmu";
+               interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10
+                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       hosc: hosc {
+               compatible = "fixed-clock";
+               clock-frequency = <24000000>;
+               #clock-cells = <0>;
+       };
+
+       losc: losc {
+               compatible = "fixed-clock";
+               clock-frequency = <32768>;
+               #clock-cells = <0>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               gic: interrupt-controller@e00f1000 {
+                       compatible = "arm,gic-400";
+                       reg = <0x0 0xe00f1000 0x0 0x1000>,
+                             <0x0 0xe00f2000 0x0 0x2000>,
+                             <0x0 0xe00f4000 0x0 0x2000>,
+                             <0x0 0xe00f6000 0x0 0x2000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+               };
+
+               uart0: serial@e0120000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0120000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART0>;
+                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart1: serial@e0122000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0122000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART1>;
+                       interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart2: serial@e0124000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0124000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART2>;
+                       interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart3: serial@e0126000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0126000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART3>;
+                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart4: serial@e0128000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe0128000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART4>;
+                       interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart5: serial@e012a000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe012a000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART5>;
+                       interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               uart6: serial@e012c000 {
+                       compatible = "actions,s900-uart", "actions,owl-uart";
+                       reg = <0x0 0xe012c000 0x0 0x2000>;
+                       clocks = <&cmu CLK_UART6>;
+                       interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               cmu: clock-controller@e0168000 {
+                       compatible = "actions,s700-cmu";
+                       reg = <0x0 0xe0168000 0x0 0x1000>;
+                       clocks = <&hosc>, <&losc>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               i2c0: i2c@e0170000 {
+                       compatible = "actions,s700-i2c";
+                       reg = <0 0xe0170000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C0>;
+                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@e0174000 {
+                       compatible = "actions,s700-i2c";
+                       reg = <0 0xe0174000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C1>;
+                       interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@e0178000 {
+                       compatible = "actions,s700-i2c";
+                       reg = <0 0xe0178000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C2>;
+                       interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c3: i2c@e017c000 {
+                       compatible = "actions,s700-i2c";
+                       reg = <0 0xe017c000 0 0x1000>;
+                       clocks = <&cmu CLK_I2C3>;
+                       interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               sps: power-controller@e01b0100 {
+                       compatible = "actions,s700-sps";
+                       reg = <0x0 0xe01b0100 0x0 0x100>;
+                       #power-domain-cells = <1>;
+               };
+
+               timer: timer@e024c000 {
+                       compatible = "actions,s700-timer";
+                       reg = <0x0 0xe024c000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "timer1";
+               };
+
+               pinctrl: pinctrl@e01b0000 {
+                       compatible = "actions,s700-pinctrl";
+                       reg = <0x0 0xe01b0000 0x0 0x1000>;
+                       clocks = <&cmu CLK_GPIO>;
+                       gpio-controller;
+                       gpio-ranges = <&pinctrl 0 0 136>;
+                       #gpio-cells = <2>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+               };
+       };
+};

diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
new file mode 100644 (file)
index 0000000..3e19429
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s700-cmu.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Device Tree binding constants for Actions Semi S700 Clock Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Author: Pathiban Nallathambi <pn@denx.de>
+ * Author: Saravanan Sekar <sravanhome@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S700_H
+#define __DT_BINDINGS_CLOCK_S700_H
+
+#define CLK_NONE                       0
+
+/* pll clocks */
+#define CLK_CORE_PLL                   1
+#define CLK_DEV_PLL                    2
+#define CLK_DDR_PLL                    3
+#define CLK_NAND_PLL                   4
+#define CLK_DISPLAY_PLL                        5
+#define CLK_TVOUT_PLL                  6
+#define CLK_CVBS_PLL                   7
+#define CLK_AUDIO_PLL                  8
+#define CLK_ETHERNET_PLL               9
+
+/* system clock */
+#define CLK_CPU                                10
+#define CLK_DEV                                11
+#define CLK_AHB                                12
+#define CLK_APB                                13
+#define CLK_DMAC                       14
+#define CLK_NOC0_CLK_MUX               15
+#define CLK_NOC1_CLK_MUX               16
+#define CLK_HP_CLK_MUX                 17
+#define CLK_HP_CLK_DIV                 18
+#define CLK_NOC1_CLK_DIV               19
+#define CLK_NOC0                       20
+#define CLK_NOC1                       21
+#define CLK_SENOR_SRC                  22
+
+/* peripheral device clock */
+#define CLK_GPIO                       23
+#define CLK_TIMER                      24
+#define CLK_DSI                                25
+#define CLK_CSI                                26
+#define CLK_SI                         27
+#define CLK_DE                         28
+#define CLK_HDE                                29
+#define CLK_VDE                                30
+#define CLK_VCE                                31
+#define CLK_NAND                       32
+#define CLK_SD0                                33
+#define CLK_SD1                                34
+#define CLK_SD2                                35
+
+#define CLK_UART0                      36
+#define CLK_UART1                      37
+#define CLK_UART2                      38
+#define CLK_UART3                      39
+#define CLK_UART4                      40
+#define CLK_UART5                      41
+#define CLK_UART6                      42
+
+#define CLK_PWM0                       43
+#define CLK_PWM1                       44
+#define CLK_PWM2                       45
+#define CLK_PWM3                       46
+#define CLK_PWM4                       47
+#define CLK_PWM5                       48
+#define CLK_GPU3D                      49
+
+#define CLK_I2C0                       50
+#define CLK_I2C1                       51
+#define CLK_I2C2                       52
+#define CLK_I2C3                       53
+
+#define CLK_SPI0                       54
+#define CLK_SPI1                       55
+#define CLK_SPI2                       56
+#define CLK_SPI3                       57
+
+#define CLK_USB3_480MPLL0              58
+#define CLK_USB3_480MPHY0              59
+#define CLK_USB3_5GPHY                 60
+#define CLK_USB3_CCE                   61
+#define CLK_USB3_MAC                   62
+
+#define CLK_LCD                                63
+#define CLK_HDMI_AUDIO                 64
+#define CLK_I2SRX                      65
+#define CLK_I2STX                      66
+
+#define CLK_SENSOR0                    67
+#define CLK_SENSOR1                    68
+
+#define CLK_HDMI_DEV                   69
+
+#define CLK_ETHERNET                   70
+#define CLK_RMII_REF                   71
+
+#define CLK_USB2H0_PLLEN               72
+#define CLK_USB2H0_PHY                 73
+#define CLK_USB2H0_CCE                 74
+#define CLK_USB2H1_PLLEN               75
+#define CLK_USB2H1_PHY                 76
+#define CLK_USB2H1_CCE                 77
+
+#define CLK_TVOUT                      78
+
+#define CLK_THERMAL_SENSOR             79
+
+#define CLK_IRC_SWITCH                 80
+#define CLK_PCM1                       81
+#define CLK_NR_CLKS                    (CLK_PCM1 + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S700_H */

diff --git a/include/dt-bindings/reset/actions,s700-reset.h b/include/dt-bindings/reset/actions,s700-reset.h
new file mode 100644 (file)
index 0000000..5e3b16b
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s700-reset.h
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+//
+// Device Tree binding constants for Actions Semi S700 Reset Management Unit
+//
+// Copyright (c) 2018 Linaro Ltd.
+
+#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H
+#define __DT_BINDINGS_ACTIONS_S700_RESET_H
+
+#define RESET_AUDIO                            0
+#define RESET_CSI                              1
+#define RESET_DE                               2
+#define RESET_DSI                              3
+#define RESET_GPIO                             4
+#define RESET_I2C0                             5
+#define RESET_I2C1                             6
+#define RESET_I2C2                             7
+#define RESET_I2C3                             8
+#define RESET_KEY                              9
+#define RESET_LCD0                             10
+#define RESET_SI                               11
+#define RESET_SPI0                             12
+#define RESET_SPI1                             13
+#define RESET_SPI2                             14
+#define RESET_SPI3                             15
+#define RESET_UART0                            16
+#define RESET_UART1                            17
+#define RESET_UART2                            18
+#define RESET_UART3                            19
+#define RESET_UART4                            20
+#define RESET_UART5                            21
+#define RESET_UART6                            22
+
+#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */