arm: dts: msm: add GENI SE QUP device tree node

On modern Qualcomm platforms including SDM845 a GENI SE QUP IP
description is supposed to be found in board device tree nodes,
the version of the IP is used by the GENI UART driver to properly
set an oversampling divider value, which impacts UART baudrate.

The change touches dragonboard845c and starqltechn board device
tree source files, a device tree node label to "debug" UART is
renamed to 'uart9' according to the naming found in Linux.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>

diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
index 1722dce33ff26c7a35bb46eb212818697b68cabb..b4f057ac6537859bcf0ab8a4e991e8059047fae2 100644 (file)
--- a/arch/arm/dts/dragonboard845c.dts
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -21,7 +21,7 @@
        };
 
        aliases {
-               serial0 = &debug_uart;
+               serial0 = &uart9;
        };
 
        memory {

diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 92bdc82177d6d058c759d7cd55b241765e090267..3b86b9328fc6dd7062ed4112cf055bb32e20b4c2 100644 (file)
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -51,16 +51,21 @@
                        };
                };
 
-               debug_uart: serial@a84000 {
-                       compatible = "qcom,geni-debug-uart";
-                       reg = <0xa84000 0x4000>;
-                       reg-names = "se_phys";
-                       clock-names = "se";
-                       clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
-                       pinctrl-names = "default";
-                       pinctrl-0 = <&qup_uart9>;
-                       qcom,wrapper-core = <0x8a>;
-                       status = "disabled";
+               qupv3_id_1: geniqup@ac0000 {
+                       compatible = "qcom,geni-se-qup";
+                       reg = <0x00ac0000 0x6000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       uart9: serial@a84000 {
+                               compatible = "qcom,geni-debug-uart";
+                               reg = <0xa84000 0x4000>;
+                               clock-names = "se";
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+                               pinctrl-names = "default";
+                               pinctrl-0 = <&qup_uart9>;
+                       };
                };
 
                spmi@c440000 {

diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
index 34a4f59cbd17b7b44d4bf8044acbf284348019ee..dcbc3b6d4966abc08766aee78d85ddacff8d9b01 100644 (file)
--- a/arch/arm/dts/starqltechn.dts
+++ b/arch/arm/dts/starqltechn.dts
@@ -21,7 +21,7 @@
        };
 
        aliases {
-               serial0 = &debug_uart;
+               serial0 = &uart9;
        };
 
        memory {