* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
+#define LOG_CATEGORY UCLASS_PHY
+
#include <common.h>
#include <clk.h>
#include <div64.h>
u32 usbphyc_pll;
if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
- pr_debug("%s: input clk freq (%dHz) out of range\n",
- __func__, clk_rate);
+ log_debug("input clk freq (%dHz) out of range\n",
+ clk_rate);
return -EINVAL;
}
writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
- pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
- clk_rate, pll_params.ndiv, pll_params.frac);
+ log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
+ clk_rate, pll_params.ndiv, pll_params.frac);
return 0;
}
true : false;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
/* Check if one phy port has already configured the pll */
if (pllen && stm32_usbphyc_is_init(usbphyc))
goto initialized;
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->init = false;
/* Check if other phy port requires pllen */
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
if (usbphyc_phy->vdd) {
ret = regulator_set_enable(usbphyc_phy->vdd, true);
if (ret)
struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
int ret;
- pr_debug("%s phy ID = %lu\n", __func__, phy->id);
+ dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
usbphyc_phy->powered = false;
if (stm32_usbphyc_is_powered(usbphyc))