i.MX8: Add crypto node in device tree

i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.

disabled use of JR1 in SPL and uboot, as JR1 is reserved
for SECO FW.

Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>

diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 7d95cf0b7dcdc2ae457e5a8b358194e55ac3c0da..63a56699b5b4b372604c9f5f82d82ae80248500a 100644 (file)
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -261,6 +261,30 @@
                                power-domains = <&pd_dma>;
                        };
                };
+
+               pd_caam: PD_CAAM {
+                       compatible = "nxp,imx8-pd";
+                       reg = <SC_R_NONE>;
+                       #power-domain-cells = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       pd_caam_jr1: PD_CAAM_JR1 {
+                               reg = <SC_R_CAAM_JR1>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_caam>;
+                       };
+                       pd_caam_jr2: PD_CAAM_JR2 {
+                               reg = <SC_R_CAAM_JR2>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_caam>;
+                       };
+                       pd_caam_jr3: PD_CAAM_JR3 {
+                               reg = <SC_R_CAAM_JR3>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_caam>;
+                       };
+               };
        };
 
        i2c0: i2c@5a800000 {
@@ -609,6 +633,41 @@
                        };
                };
        };
+
+       crypto: caam@0x31400000 {
+               compatible = "fsl,sec-v4.0";
+               reg = <0 0x31400000 0 0x400000>;
+               interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0 0x31400000 0x400000>;
+               fsl,first-jr-index = <2>;
+               fsl,sec-era = <9>;
+
+               sec_jr1: jr1@0x20000 {
+                       compatible = "fsl,sec-v4.0-job-ring";
+                       reg = <0x20000 0x1000>;
+                       interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&pd_caam_jr1>;
+                       status = "disabled";
+               };
+
+               sec_jr2: jr2@30000 {
+                       compatible = "fsl,sec-v4.0-job-ring";
+                       reg = <0x30000 0x1000>;
+                       interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&pd_caam_jr2>;
+                       status = "okay";
+               };
+
+               sec_jr3: jr3@40000 {
+                       compatible = "fsl,sec-v4.0-job-ring";
+                       reg = <0x40000 0x1000>;
+                       interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&pd_caam_jr3>;
+                       status = "okay";
+               };
+       };
 };
 
 &A35_0 {

diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 9e0d264b71f5cf82592181ced0ccf011912277df..a95209e141950c25382b222387c4728ccffe331a 100644 (file)
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 &{/imx8qm-pm} {
@@ -80,6 +80,22 @@
        u-boot,dm-spl;
 };
 
+&pd_caam {
+       u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+       u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+       u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+       u-boot,dm-spl;
+};
+
 &gpio0 {
        u-boot,dm-spl;
 };
@@ -126,3 +142,19 @@
        sd-uhs-sdr104;
        sd-uhs-ddr50;
 };
+
+&crypto {
+       u-boot,dm-spl;
+};
+
+&sec_jr1 {
+       u-boot,dm-spl;
+};
+
+&sec_jr2 {
+       u-boot,dm-spl;
+};
+
+&sec_jr3 {
+       u-boot,dm-spl;
+};

diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index 88aeaf65b31c72b4efbbe47a4583bd03e8cc88bf..517fb13cad64c7997ef9bb70ab8b610a5ff278cf 100644 (file)
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -235,6 +235,30 @@
                                wakeup-irq = <349>;
                        };
                };
+
+               pd_caam: PD_CAAM {
+                       compatible = "nxp,imx8-pd";
+                       reg = <SC_R_NONE>;
+                       #power-domain-cells = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       pd_caam_jr1: PD_CAAM_JR1 {
+                               reg = <SC_R_CAAM_JR1>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_caam>;
+                       };
+                       pd_caam_jr2: PD_CAAM_JR2 {
+                               reg = <SC_R_CAAM_JR2>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_caam>;
+                       };
+                       pd_caam_jr3: PD_CAAM_JR3 {
+                               reg = <SC_R_CAAM_JR3>;
+                               #power-domain-cells = <0>;
+                               power-domains = <&pd_caam>;
+                       };
+               };
        };
 
        i2c0: i2c@5a800000 {
@@ -556,6 +580,41 @@
                power-domains = <&pd_conn_enet1>;
                status = "disabled";
        };
+
+       crypto: caam@0x31400000 {
+               compatible = "fsl,sec-v4.0";
+               reg = <0 0x31400000 0 0x400000>;
+               interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0 0x31400000 0x400000>;
+               fsl,first-jr-index = <2>;
+               fsl,sec-era = <9>;
+
+               sec_jr1: jr1@0x20000 {
+                       compatible = "fsl,sec-v4.0-job-ring";
+                       reg = <0x20000 0x1000>;
+                       interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&pd_caam_jr1>;
+                       status = "disabled";
+               };
+
+               sec_jr2: jr2@30000 {
+                       compatible = "fsl,sec-v4.0-job-ring";
+                       reg = <0x30000 0x1000>;
+                       interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&pd_caam_jr2>;
+                       status = "okay";
+               };
+
+               sec_jr3: jr3@40000 {
+                       compatible = "fsl,sec-v4.0-job-ring";
+                       reg = <0x40000 0x1000>;
+                       interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
+                       power-domains = <&pd_caam_jr3>;
+                       status = "okay";
+               };
+       };
 };
 
 &A53_0 {

diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
index 701af4434d56f95bbc66158a8a0d7ee5b16e472d..ae037c7550df5b7256e345fcc7c1a4ee98244249 100644 (file)
--- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
  */
 
 &{/imx8qx-pm} {
@@ -80,6 +80,22 @@
        u-boot,dm-spl;
 };
 
+&pd_caam {
+       u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+       u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+       u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+       u-boot,dm-spl;
+};
+
 &gpio0 {
        u-boot,dm-spl;
 };
@@ -126,3 +142,19 @@
        sd-uhs-sdr104;
        sd-uhs-ddr50;
 };
+
+&crypto {
+       u-boot,dm-spl;
+};
+
+&sec_jr1 {
+       u-boot,dm-spl;
+};
+
+&sec_jr2 {
+       u-boot,dm-spl;
+};
+
+&sec_jr3 {
+       u-boot,dm-spl;
+};