dm: x86: queensbay: Add an interrupt driver

Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile
index 660f9678bd303573ef506986f913382c4377e002..af3ffad385222ffb8ecafaca28d71d3b13eaba0e 100644 (file)
--- a/arch/x86/cpu/queensbay/Makefile
+++ b/arch/x86/cpu/queensbay/Makefile
@@ -4,5 +4,5 @@
 # SPDX-License-Identifier:     GPL-2.0+
 #
 
-obj-y += fsp_configs.o
+obj-y += fsp_configs.o irq.o
 obj-y += tnc.o topcliff.o

diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
new file mode 100644 (file)
index 0000000..44369f7
--- /dev/null
+++ b/arch/x86/cpu/queensbay/irq.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/pci.h>
+#include <asm/arch/device.h>
+#include <asm/arch/tnc.h>
+
+int queensbay_irq_router_probe(struct udevice *dev)
+{
+       struct tnc_rcba *rcba;
+       u32 base;
+
+       base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+       base &= ~MEM_BAR_EN;
+       rcba = (struct tnc_rcba *)base;
+
+       /* Make sure all internal PCI devices are using INTA */
+       writel(INTA, &rcba->d02ip);
+       writel(INTA, &rcba->d03ip);
+       writel(INTA, &rcba->d27ip);
+       writel(INTA, &rcba->d31ip);
+       writel(INTA, &rcba->d23ip);
+       writel(INTA, &rcba->d24ip);
+       writel(INTA, &rcba->d25ip);
+       writel(INTA, &rcba->d26ip);
+
+       /*
+        * Route TunnelCreek PCI device interrupt pin to PIRQ
+        *
+        * Since PCIe downstream ports received INTx are routed to PIRQ
+        * A/B/C/D directly and not configurable, we have to route PCIe
+        * root ports' INTx to PIRQ A/B/C/D as well. For other devices
+        * on TunneCreek, route them to PIRQ E/F/G/H.
+        */
+       writew(PIRQE, &rcba->d02ir);
+       writew(PIRQF, &rcba->d03ir);
+       writew(PIRQG, &rcba->d27ir);
+       writew(PIRQH, &rcba->d31ir);
+       writew(PIRQA, &rcba->d23ir);
+       writew(PIRQB, &rcba->d24ir);
+       writew(PIRQC, &rcba->d25ir);
+       writew(PIRQD, &rcba->d26ir);
+
+       return irq_router_common_init(dev);
+}
+
+static const struct udevice_id queensbay_irq_router_ids[] = {
+       { .compatible = "intel,queensbay-irq-router" },
+       { }
+};
+
+U_BOOT_DRIVER(queensbay_irq_router_drv) = {
+       .name           = "queensbay_intel_irq",
+       .id             = UCLASS_IRQ,
+       .of_match       = queensbay_irq_router_ids,
+       .probe          = queensbay_irq_router_probe,
+};

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index b65906b6c565e49317c478d50e51359550ca24f6..75f7adb74cd622603c595cd228930a09a45e01f8 100644 (file)
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -69,43 +69,6 @@ int arch_early_init_r(void)
        return 0;
 }
 
-void cpu_irq_init(void)
-{
-       struct tnc_rcba *rcba;
-       u32 base;
-
-       base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
-       base &= ~MEM_BAR_EN;
-       rcba = (struct tnc_rcba *)base;
-
-       /* Make sure all internal PCI devices are using INTA */
-       writel(INTA, &rcba->d02ip);
-       writel(INTA, &rcba->d03ip);
-       writel(INTA, &rcba->d27ip);
-       writel(INTA, &rcba->d31ip);
-       writel(INTA, &rcba->d23ip);
-       writel(INTA, &rcba->d24ip);
-       writel(INTA, &rcba->d25ip);
-       writel(INTA, &rcba->d26ip);
-
-       /*
-        * Route TunnelCreek PCI device interrupt pin to PIRQ
-        *
-        * Since PCIe downstream ports received INTx are routed to PIRQ
-        * A/B/C/D directly and not configurable, we have to route PCIe
-        * root ports' INTx to PIRQ A/B/C/D as well. For other devices
-        * on TunneCreek, route them to PIRQ E/F/G/H.
-        */
-       writew(PIRQE, &rcba->d02ir);
-       writew(PIRQF, &rcba->d03ir);
-       writew(PIRQG, &rcba->d27ir);
-       writew(PIRQH, &rcba->d31ir);
-       writew(PIRQA, &rcba->d23ir);
-       writew(PIRQB, &rcba->d24ir);
-       writew(PIRQC, &rcba->d25ir);
-       writew(PIRQD, &rcba->d26ir);
-}
-
 int arch_misc_init(void)
 {
        unprotect_spi_flash();

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 2a18be065e3b7f9f8057a0d0c56b218937429b3d..d6dd0b49f0fac3a64f9ec4192c3a2ed431d2610f 100644 (file)
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -164,7 +164,7 @@
                        compatible = "intel,pch7";
 
                        irq-router {
-                               compatible = "intel,irq-router";
+                               compatible = "intel,queensbay-irq-router";
                                intel,pirq-config = "pci";
                                intel,pirq-link = <0x60 8>;
                                intel,pirq-mask = <0xcee0>;