select OF_LIVE
select BOARD_LATE_INIT
select SYS_CACHE_SHIFT_7
+
+config ARCH_OCTEONTX2
+ bool "Support OcteonTX2 SoCs"
+ select DM
+ select ARM64
+ select OF_CONTROL
+ select OF_LIVE
+ select BOARD_LATE_INIT
+ select SYS_CACHE_SHIFT_7
+
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
select ARM64
source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-octeontx/Kconfig"
+
+source "arch/arm/mach-octeontx2/Kconfig"
+
source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/gplugd/Kconfig"
source "board/Marvell/octeontx/Kconfig"
+source "board/Marvell/octeontx2/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
machine-$(CONFIG_ARCH_TEGRA) += tegra
machine-$(CONFIG_ARCH_U8500) += u8500
machine-$(CONFIG_ARCH_OCTEONTX) += octeontx
+machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSAL) += versal
machine-$(CONFIG_ARCH_ZYNQ) += zynq
--- /dev/null
+if ARCH_OCTEONTX2
+
+choice
+ prompt "OcteonTX2 board select"
+ optional
+
+config TARGET_OCTEONTX2_95XX
+ bool "Marvell OcteonTX2 CN95XX"
+
+config TARGET_OCTEONTX2_96XX
+ bool "Marvell OcteonTX2 CN96XX"
+
+endchoice
+
+config SYS_SOC
+ string
+ default "octeontx2"
+
+config SYS_PCI_64BIT
+ bool
+ default y
+
+endif
--- /dev/null
+#/*
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * SPDX-License-Identifier: GPL-2.0
+# * https://spdx.org/licenses
+# */
+
+obj-y += lowlevel_init.o clock.o cpu.o
+
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+#include <asm/arch/clock.h>
+
+/**
+ * Returns the I/O clock speed in Hz
+ */
+u64 octeontx_get_io_clock(void)
+{
+ union rst_boot rst_boot;
+
+ rst_boot.u = readq(RST_BOOT);
+
+ return rst_boot.s.pnr_mul * PLL_REF_CLK;
+}
+
+/**
+ * Returns the core clock speed in Hz
+ */
+u64 octeontx_get_core_clock(void)
+{
+ union rst_boot rst_boot;
+
+ rst_boot.u = readq(RST_BOOT);
+
+ return rst_boot.s.c_mul * PLL_REF_CLK;
+}
--- /dev/null
+ifeq ($(CONFIG_ARCH_OCTEONTX2),y)
+PLATFORM_CPPFLAGS += $(call cc-option,-march=armv8.2-a,)
+PLATFORM_CPPFLAGS += $(call cc-option,-mtune=octeontx2,)
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/board.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define OTX2_MEM_MAP_USED 4
+
+/* +1 is end of list which needs to be empty */
+#define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
+
+static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = {
+ {
+ .virt = 0x800000000000UL,
+ .phys = 0x800000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x840000000000UL,
+ .phys = 0x840000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x880000000000UL,
+ .phys = 0x880000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }, {
+ .virt = 0x8c0000000000UL,
+ .phys = 0x8c0000000000UL,
+ .size = 0x40000000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ }
+};
+
+struct mm_region *mem_map = otx2_mem_map;
+
+void mem_map_fill(void)
+{
+ int banks = OTX2_MEM_MAP_USED;
+ u32 dram_start = CONFIG_SYS_TEXT_BASE;
+
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ otx2_mem_map[banks].virt = dram_start;
+ otx2_mem_map[banks].phys = dram_start;
+ otx2_mem_map[banks].size = gd->ram_size;
+ otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_NON_SHARE;
+ banks = banks + 1;
+ }
+}
+
+u64 get_page_table_size(void)
+{
+ return 0x80000;
+}
+
+void reset_cpu(ulong addr)
+{
+}
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+.align 8
+.global fdt_base_addr
+fdt_base_addr:
+ .dword 0x0
+
+.global save_boot_params
+save_boot_params:
+ /* Read FDT base from x1 register passed by ATF */
+ adr x21, fdt_base_addr
+ str x1, [x21]
+
+ /* Returns */
+ b save_boot_params_ret
+
+ENTRY(lowlevel_init)
+ mov x29, lr /* Save LR */
+
+ /* any lowlevel init should go here */
+
+ mov lr, x29 /* Restore LR */
+ ret
+ENDPROC(lowlevel_init)
--- /dev/null
+if TARGET_OCTEONTX2_95XX || TARGET_OCTEONTX2_96XX
+
+config SYS_VENDOR
+ string
+ default "Marvell"
+
+config SYS_BOARD
+ string
+ default "octeontx2"
+
+config SYS_CONFIG_NAME
+ default "octeontx2_common"
+
+endif
--- /dev/null
+OCTEONTX2 BOARD
+M: Aaron Williams <awilliams@marvell.com>
+S: Maintained
+F: board/Marvell/octeontx2/
+F: include/configs/octeontx2_96xx.h
+F: include/configs/octeontx2_95xx.h
+F: configs/octeontx2_96xx_defconfig
+F: configs/octeontx2_95xx_defconfig
--- /dev/null
+#/* SPDX-License-Identifier: GPL-2.0
+# *
+# * Copyright (C) 2018 Marvell International Ltd.
+# *
+# * https://spdx.org/licenses
+# */
+
+obj-y := board.o smc.o soc-utils.o
+obj-$(CONFIG_OF_LIBFDT) += board-fdt.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <errno.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <log.h>
+
+#include <linux/compiler.h>
+#include <linux/libfdt.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/smc.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int fdt_get_bdk_node(void)
+{
+ int node, ret;
+ const void *fdt = gd->fdt_blob;
+
+ if (!fdt) {
+ printf("ERROR: %s: no valid device tree found\n", __func__);
+ return 0;
+ }
+
+ ret = fdt_check_header(fdt);
+ if (ret < 0) {
+ printf("fdt: %s\n", fdt_strerror(ret));
+ return 0;
+ }
+
+ node = fdt_path_offset(fdt, "/cavium,bdk");
+ if (node < 0) {
+ printf("%s: /cavium,bdk is missing from device tree: %s\n",
+ __func__, fdt_strerror(node));
+ return 0;
+ }
+ return node;
+}
+
+u64 fdt_get_board_mac_addr(void)
+{
+ int node, len = 16;
+ const char *str = NULL;
+ const void *fdt = gd->fdt_blob;
+ u64 mac_addr = 0;
+
+ node = fdt_get_bdk_node();
+ if (!node)
+ return mac_addr;
+ str = fdt_getprop(fdt, node, "BOARD-MAC-ADDRESS", &len);
+ if (str)
+ mac_addr = simple_strtol(str, NULL, 16);
+ return mac_addr;
+}
+
+int fdt_get_board_mac_cnt(void)
+{
+ int node, len = 16;
+ const char *str = NULL;
+ const void *fdt = gd->fdt_blob;
+ int mac_count = 0;
+
+ node = fdt_get_bdk_node();
+ if (!node)
+ return mac_count;
+ str = fdt_getprop(fdt, node, "BOARD-MAC-ADDRESS-NUM", &len);
+ if (str) {
+ mac_count = simple_strtol(str, NULL, 10);
+ if (!mac_count)
+ mac_count = simple_strtol(str, NULL, 16);
+ debug("fdt: MAC_NUM %d\n", mac_count);
+ } else {
+ printf("Error: cannot retrieve mac count prop from fdt\n");
+ }
+ str = fdt_getprop(gd->fdt_blob, node, "BOARD-MAC-ADDRESS-NUM-OVERRIDE",
+ &len);
+ if (str) {
+ if (simple_strtol(str, NULL, 10) >= 0)
+ mac_count = simple_strtol(str, NULL, 10);
+ debug("fdt: MAC_NUM %d\n", mac_count);
+ } else {
+ printf("Error: cannot retrieve mac num override prop\n");
+ }
+ return mac_count;
+}
+
+const char *fdt_get_board_serial(void)
+{
+ const void *fdt = gd->fdt_blob;
+ int node, len = 64;
+ const char *str = NULL;
+
+ node = fdt_get_bdk_node();
+ if (!node)
+ return NULL;
+
+ str = fdt_getprop(fdt, node, "BOARD-SERIAL", &len);
+ if (!str)
+ printf("Error: cannot retrieve board serial from fdt\n");
+ return str;
+}
+
+const char *fdt_get_board_revision(void)
+{
+ const void *fdt = gd->fdt_blob;
+ int node, len = 64;
+ const char *str = NULL;
+
+ node = fdt_get_bdk_node();
+ if (!node)
+ return NULL;
+
+ str = fdt_getprop(fdt, node, "BOARD-REVISION", &len);
+ if (!str)
+ printf("Error: cannot retrieve board revision from fdt\n");
+ return str;
+}
+
+const char *fdt_get_board_model(void)
+{
+ int node, len = 16;
+ const char *str = NULL;
+ const void *fdt = gd->fdt_blob;
+
+ node = fdt_get_bdk_node();
+ if (!node)
+ return NULL;
+ str = fdt_getprop(fdt, node, "BOARD-MODEL", &len);
+ if (!str)
+ printf("Error: cannot retrieve board model from fdt\n");
+ return str;
+}
+
+int arch_fixup_memory_node(void *blob)
+{
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ int nodeoff, node, ret, i;
+ const char *temp;
+
+ static const char * const
+ octeontx_brd_nodes[] = {"BOARD-MODEL",
+ "BOARD-SERIAL",
+ "BOARD-MAC-ADDRESS",
+ "BOARD-REVISION",
+ "BOARD-MAC-ADDRESS-NUM"
+ };
+ char nodes[ARRAY_SIZE(octeontx_brd_nodes)][32];
+
+ ret = fdt_check_header(blob);
+ if (ret < 0) {
+ printf("ERROR: %s\n", fdt_strerror(ret));
+ return ret;
+ }
+
+ if (blob) {
+ nodeoff = fdt_path_offset(blob, "/cavium,bdk");
+ if (nodeoff < 0) {
+ printf("ERROR: FDT BDK node not found\n");
+ return nodeoff;
+ }
+
+ /* Read properties in temporary variables */
+ for (i = 0; i < ARRAY_SIZE(octeontx_brd_nodes); i++) {
+ temp = fdt_getprop(blob, nodeoff,
+ octeontx_brd_nodes[i], NULL);
+ strncpy(nodes[i], temp, sizeof(nodes[i]));
+ }
+
+ /* Delete cavium,bdk node */
+ ret = fdt_del_node(blob, nodeoff);
+ if (ret < 0) {
+ printf("WARNING : could not remove cavium, bdk node\n");
+ return ret;
+ }
+ debug("%s deleted 'cavium,bdk' node\n", __func__);
+ /*
+ * Add a new node at root level which would have
+ * necessary info
+ */
+ node = fdt_add_subnode(blob, 0, "octeontx_brd");
+ if (node < 0) {
+ printf("Cannot create node octeontx_brd: %s\n",
+ fdt_strerror(node));
+ return -EIO;
+ }
+
+ /* Populate properties in node */
+ for (i = 0; i < ARRAY_SIZE(octeontx_brd_nodes); i++) {
+ if (fdt_setprop_string(blob, node,
+ octeontx_brd_nodes[i],
+ nodes[i])) {
+ printf("Can't set %s\n", nodes[i]);
+ return -EIO;
+ }
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * Return the FDT base address that was passed by ATF
+ *
+ * @return FDT base address received from ATF in x1 register
+ */
+void *board_fdt_blob_setup(void)
+{
+ return (void *)fdt_base_addr;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <command.h>
+#include <console.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <net.h>
+#include <pci_ids.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/arch/smc.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/board.h>
+#include <dm/util.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void cleanup_env_ethaddr(void)
+{
+ char ename[32];
+
+ for (int i = 0; i < 20; i++) {
+ sprintf(ename, i ? "eth%daddr" : "ethaddr", i);
+ if (env_get(ename))
+ env_set(ename, NULL);
+ }
+}
+
+void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr)
+{
+ u64 tmp_mac, board_mac_addr = fdt_get_board_mac_addr();
+ static int board_mac_num;
+
+ board_mac_num = fdt_get_board_mac_cnt();
+ if ((!is_zero_ethaddr((u8 *)&board_mac_addr)) && board_mac_num) {
+ tmp_mac = board_mac_addr;
+ tmp_mac += index;
+ tmp_mac = swab64(tmp_mac) >> 16;
+ memcpy(mac_addr, (u8 *)&tmp_mac, ARP_HLEN);
+ board_mac_num--;
+ } else {
+ memset(mac_addr, 0, ARP_HLEN);
+ }
+ debug("%s mac %pM\n", __func__, mac_addr);
+}
+
+void board_quiesce_devices(void)
+{
+ struct uclass *uc_dev;
+ int ret;
+
+ /* Removes all RVU PF devices */
+ ret = uclass_get(UCLASS_ETH, &uc_dev);
+ if (uc_dev)
+ ret = uclass_destroy(uc_dev);
+ if (ret)
+ printf("couldn't remove rvu pf devices\n");
+
+ if (IS_ENABLED(CONFIG_OCTEONTX2_CGX_INTF)) {
+ /* Bring down all cgx lmac links */
+ cgx_intf_shutdown();
+ }
+
+ /* Removes all CGX and RVU AF devices */
+ ret = uclass_get(UCLASS_MISC, &uc_dev);
+ if (uc_dev)
+ ret = uclass_destroy(uc_dev);
+ if (ret)
+ printf("couldn't remove misc (cgx/rvu_af) devices\n");
+
+ /* SMC call - removes all LF<->PF mappings */
+ smc_disable_rvu_lfs(0);
+}
+
+int board_early_init_r(void)
+{
+ pci_init();
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+int timer_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = smc_dram_size(0);
+ gd->ram_size -= CONFIG_SYS_SDRAM_BASE;
+
+ mem_map_fill();
+
+ return 0;
+}
+
+void board_late_probe_devices(void)
+{
+ struct udevice *dev;
+ int err, cgx_cnt = 3, i;
+
+ /* Probe MAC(CGX) and NIC AF devices before Network stack init */
+ for (i = 0; i < cgx_cnt; i++) {
+ err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVICE_ID_CAVIUM_CGX, i, &dev);
+ if (err)
+ debug("%s CGX%d device not found\n", __func__, i);
+ }
+ err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVICE_ID_CAVIUM_RVU_AF, 0, &dev);
+ if (err)
+ debug("NIC AF device not found\n");
+}
+
+/**
+ * Board late initialization routine.
+ */
+int board_late_init(void)
+{
+ char boardname[32];
+ char boardserial[150], boardrev[150];
+ long val;
+ bool save_env = false;
+ const char *str;
+
+ debug("%s()\n", __func__);
+
+ /*
+ * Now that pci_init initializes env device.
+ * Try to cleanup ethaddr env variables, this is needed
+ * as with each boot, configuration of QLM can change.
+ */
+ cleanup_env_ethaddr();
+
+ snprintf(boardname, sizeof(boardname), "%s> ", fdt_get_board_model());
+ env_set("prompt", boardname);
+ set_working_fdt_addr(env_get_hex("fdtcontroladdr", fdt_base_addr));
+
+ str = fdt_get_board_revision();
+ if (str) {
+ snprintf(boardrev, sizeof(boardrev), "%s", str);
+ if (env_get("boardrev") &&
+ strcmp(boardrev, env_get("boardrev")))
+ save_env = true;
+ env_set("boardrev", boardrev);
+ }
+
+ str = fdt_get_board_serial();
+ if (str) {
+ snprintf(boardserial, sizeof(boardserial), "%s", str);
+ if (env_get("serial#") &&
+ strcmp(boardserial, env_get("serial#")))
+ save_env = true;
+ env_set("serial#", boardserial);
+ }
+
+ val = env_get_hex("disable_ooo", 0);
+ smc_configure_ooo(val);
+
+ if (IS_ENABLED(CONFIG_NET_OCTEONTX2))
+ board_late_probe_devices();
+
+ if (save_env)
+ env_save();
+
+ return 0;
+}
+
+/*
+ * Invoked before relocation, so limit to stack variables.
+ */
+int checkboard(void)
+{
+ printf("Board: %s\n", fdt_get_board_model());
+
+ return 0;
+}
+
+void board_acquire_flash_arb(bool acquire)
+{
+ union cpc_boot_ownerx ownerx;
+
+ if (!acquire) {
+ ownerx.u = readl(CPC_BOOT_OWNERX(3));
+ ownerx.s.boot_req = 0;
+ writel(ownerx.u, CPC_BOOT_OWNERX(3));
+ } else {
+ ownerx.u = 0;
+ ownerx.s.boot_req = 1;
+ writel(ownerx.u, CPC_BOOT_OWNERX(3));
+ udelay(1);
+ do {
+ ownerx.u = readl(CPC_BOOT_OWNERX(3));
+ } while (ownerx.s.boot_wait);
+ }
+}
+
+int last_stage_init(void)
+{
+ (void)smc_flsf_fw_booted();
+ return 0;
+}
+
+static int do_go_uboot(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ typedef void __noreturn (*uboot_entry_t)(ulong, void *);
+ uboot_entry_t entry;
+ ulong addr;
+ void *fdt;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[1], NULL, 16);
+ fdt = board_fdt_blob_setup();
+ entry = (uboot_entry_t)addr;
+ flush_cache((ulong)addr, 1 << 20); /* 1MiB should be enough */
+ dcache_disable();
+
+ printf("## Starting U-Boot at %p (FDT at %p)...\n", entry, fdt);
+
+ entry(0, fdt);
+
+ return 0;
+}
+
+U_BOOT_CMD(go_uboot, 2, 0, do_go_uboot,
+ "Start U-Boot from RAM (pass FDT via x1 register)",
+ "");
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/psci.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/arch/smc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+ssize_t smc_dram_size(unsigned int node)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = OCTEONTX2_DRAM_SIZE;
+ regs.regs[1] = node;
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t smc_disable_rvu_lfs(unsigned int node)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = OCTEONTX2_DISABLE_RVU_LFS;
+ regs.regs[1] = node;
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t smc_configure_ooo(unsigned int val)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = OCTEONTX2_CONFIG_OOO;
+ regs.regs[1] = val;
+ smc_call(®s);
+
+ return regs.regs[0];
+}
+
+ssize_t smc_flsf_fw_booted(void)
+{
+ struct pt_regs regs;
+
+ regs.regs[0] = OCTEONTX2_FSAFE_PR_BOOT_SUCCESS;
+ smc_call(®s);
+
+ return regs.regs[0];
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/board.h>
+#include <dm/util.h>
+
+int read_platform(void)
+{
+ int plat = PLATFORM_HW;
+
+ const char *model = fdt_get_board_model();
+
+ if (model && !strncmp(model, "ASIM-", 5))
+ plat = PLATFORM_ASIM;
+ if (model && !strncmp(model, "EMUL-", 5))
+ plat = PLATFORM_EMULATOR;
+
+ return plat;
+}
+
+static inline u64 read_midr(void)
+{
+ u64 result;
+
+ asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result));
+ return result;
+}
+
+u8 read_partnum(void)
+{
+ return ((read_midr() >> 4) & 0xFF);
+}
+
+const char *read_board_name(void)
+{
+ return fdt_get_board_model();
+}
+
--- /dev/null
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_OCTEONTX2=y
+CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x8000
+CONFIG_ENV_OFFSET=0xF00000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_OCTEONTX2_95XX=y
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0x87e028000000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=6 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Marvell> "
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_MEMTEST_START=0x04000000
+CONFIG_SYS_MEMTEST_END=0x040f0000
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=125000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_I2C=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_OCTEONTX=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=125000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_NET_OCTEONTX2=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCI_SRIOV=y
+CONFIG_PCI_ARID=y
+CONFIG_PCI_OCTEONTX=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_WDT=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+CONFIG_ARM=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+CONFIG_ARCH_OCTEONTX2=y
+CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x8000
+CONFIG_ENV_OFFSET=0xF00000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_TARGET_OCTEONTX2_96XX=y
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0x87e028000000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M"
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="Marvell> "
+# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MX_CYCLIC=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_SHA1SUM_VERIFY=y
+CONFIG_CMD_DM=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_PXE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USE_ENV_SPI_BUS=y
+CONFIG_ENV_SPI_BUS=0
+CONFIG_USE_ENV_SPI_CS=y
+CONFIG_ENV_SPI_CS=0
+CONFIG_USE_ENV_SPI_MAX_HZ=y
+CONFIG_ENV_SPI_MAX_HZ=125000000
+CONFIG_USE_ENV_SPI_MODE=y
+CONFIG_ENV_SPI_MODE=0x0
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SCSI_AHCI=y
+CONFIG_AHCI_PCI=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_OCTEONTX=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=125000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_VITESSE=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_E1000_SPI=y
+CONFIG_CMD_E1000=y
+CONFIG_NET_OCTEONTX2=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_REGION_MULTI_ENTRY=y
+CONFIG_PCI_SRIOV=y
+CONFIG_PCI_ARID=y
+CONFIG_PCI_OCTEONTX=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_PL01X_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_OCTEON_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_WDT=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * https://spdx.org/licenses
+ */
+
+#ifndef __OCTEONTX2_COMMON_H__
+#define __OCTEONTX2_COMMON_H__
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/** Maximum size of image supported for bootm (and bootable FIT images) */
+#define CONFIG_SYS_BOOTM_LEN (256 << 20)
+
+/** Memory base address */
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE
+
+/** Stack starting address */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0)
+
+/** Heap size for U-Boot */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024)
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_LAST_STAGE_INIT
+
+/* Allow environment variable to be overwritten */
+#define CONFIG_ENV_OVERWRITE
+
+/** Reduce hashes printed out */
+#define CONFIG_TFTP_TSIZE
+
+/* Autoboot options */
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_BOOT_RETRY_TIME -1
+#define CONFIG_BOOT_RETRY_MIN 30
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/** Extra environment settings */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=20080000\0" \
+ "ethrotate=yes\0" \
+ "autoload=0\0"
+
+/** Environment defines */
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MAXARGS 64 /** max command args */
+
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT env_get("prompt")
+
+#if defined(CONFIG_MMC_OCTEONTX)
+#define MMC_SUPPORTS_TUNING
+/** EMMC specific defines */
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_CMD_BKOPS_ENABLE
+#endif
+
+#endif /* __OCTEONTX2_COMMON_H__ */
projects / u-boot.git / commitdiff