arm: mvebu: AXP: Enhance PCIe port capability configuration

This patch enables the PCIe port specific link capabilities configuration
for Armada XP. The weak function board_sat_r_get() was used to return
a common flag for PCIe Gen1 vs Gen2 capability for all PCIe ports. This
is now changed with this patch to return a bit per PCIe port (4 bits
in this case, bit 0 for PCIe port 0, etc).

The theadorable board uses this new feature to configure PCIe port 0
as Gen1 and all other PCIe ports as Gen2 capable. All other AXP boards
using this function are not changed in the configuration and still
configure all ports as PCIe Gen2.

This patch also removes the parameter "pex_mode" from
board_serdes_cfg_get() as this parameter was not used in any of the
implementations.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Phil Sutter <phil@nwl.cc>

diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
index 569840ff47186da2b38c2ce7f83c50479f7e4c1b..c8c92988645f27e4f6c02f8f3cd9c72408b28983 100644 (file)
--- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
+++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c
@@ -35,7 +35,7 @@ int pex_local_dev_num_set(u32 pex_if, u32 dev_num);
 #define        ETM_MODULE_DETECT               2
 
 #define PEX_MODE_GET(satr)             ((satr & 0x6) >> 1)
-#define PEX_CAPABILITY_GET(satr)       (satr & 1)
+#define PEX_CAPABILITY_GET(satr, port) ((satr >> port) & 1)
 #define MV_PEX_UNIT_TO_IF(pex_unit)    ((pex_unit < 3) ? (pex_unit * 4) : 9)
 
 /* Static parametes */
@@ -176,7 +176,7 @@ u8 board_cpu_freq_get(void)
        return ((sar_msb & 0x100000) >> 17) | ((sar & 0xe00000) >> 21);
 }
 
-__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+__weak MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
 {
        u32 board_id;
        u32 serdes_cfg_val = 0; /* default */
@@ -352,7 +352,7 @@ int serdes_phy_config(void)
                DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs);
        }
 
-       info = board_serdes_cfg_get(PEX_MODE_GET(satr11));
+       info = board_serdes_cfg_get();
 
        if (info == NULL) {
                DEBUG_INIT_S("Hight speed PHY Error #1\n");
@@ -675,7 +675,7 @@ int serdes_phy_config(void)
                                tmp |= (0x1 << 4);
                        if (info->pex_mode[pex_unit] == PEX_BUS_MODE_X4)
                                tmp |= (0x4 << 4);
-                       if (0 == PEX_CAPABILITY_GET(satr11))
+                       if (0 == PEX_CAPABILITY_GET(satr11, pex_unit))
                                tmp |= 0x1;
                        else
                                tmp |= 0x2;

diff --git a/board/Synology/ds414/ds414.c b/board/Synology/ds414/ds414.c
index eb3694ea6e7c23eae75a3008b2cd01700513e149..d23e97c9b9165b3aafe2f8983538a4d1a7d73275 100644 (file)
--- a/board/Synology/ds414/ds414.c
+++ b/board/Synology/ds414/ds414.c
@@ -115,14 +115,14 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
        return &ds414_ddr_modes[0];
 }
 
-MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
 {
        return &ds414_serdes_cfg[0];
 }
 
 u8 board_sat_r_get(u8 dev_num, u8 reg)
 {
-       return (0x1 << 1 | 1);
+       return 0xf;     /* All PEX ports support PCIe Gen2 */
 }
 
 int board_early_init_f(void)

diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c
index e8f8f7ba5b4775826ec4a190f46f74804f50625e..395904f8c87861648c214156c785736c6812e0f4 100644 (file)
--- a/board/maxbcm/maxbcm.c
+++ b/board/maxbcm/maxbcm.c
@@ -95,7 +95,7 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
        return &maxbcm_ddr_modes[0];
 }
 
-MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
 {
        return &maxbcm_serdes_cfg[0];
 }

diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index 7b9c706cd47bf9229e6a011aa1deb34b5805d409..d42350319cc4f2c9905443a143135a4c191ffc3c 100644 (file)
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -132,15 +132,15 @@ MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
        return &board_ddr_modes[0];
 }
 
-MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(void)
 {
        return &theadorable_serdes_cfg[0];
 }
 
 u8 board_sat_r_get(u8 dev_num, u8 reg)
 {
-       /* Bit 0 enables PCI 2.0 link capabilities instead of PCI 1.x */
-       return 0x01;
+       /* Bit x enables PCI 2.0 link capabilities instead of PCI 1.x */
+       return 0xe;     /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */
 }
 
 int board_early_init_f(void)