clk: rockchip: rk3399: Set 50MHz ddr clock

Add support for setting 50MHz ddr clock.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 69a887f70cf17e886db1da251e80d334c958a032..2c001661e1e7c9578d2781ba17724ea6b0f468df 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 
        /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
        switch (set_rate) {
+       case 50 * MHz:
+               dpll_cfg = (struct pll_div)
+               {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
+               break;
        case 200 * MHz:
                dpll_cfg = (struct pll_div)
                {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};