arm: socfpga: spl: enable sdram, timer and uart

Add the calls in the spl_board_init to enable SDRAM, timer, and UART.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>

diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 6a8c15d91fbcaba9f404aab42c47dac38a488d42..a4dbe4ffe61fb75be5ea83f915e1fd0c59224ab9 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -144,6 +144,10 @@ void spl_board_init(void)
        /* freeze all IO banks */
        sys_mgr_frzctrl_freeze_req();
 
+       socfpga_sdram_enable();
+       socfpga_uart0_enable();
+       socfpga_osc1timer_enable();
+
        debug("Reconfigure Clock Manager\n");
        /* reconfigure the PLLs */
        cm_basic_init(&cm_default_cfg);