armv8/fsl-lsch3: Set nodes in DVM domain

This is required for TLB invalidation broadcasts to work.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 53bdb4487cc0d8dab5120155e649f480b1e3969b..018c61742ee8fd4a3b1e3ade9ac7cccc338a022e 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -15,6 +15,15 @@
 ENTRY(lowlevel_init)
        mov     x29, lr                 /* Save LR */
 
+       /* Add fully-coherent masters to DVM domain */
+       ldr     x1, =CCI_MN_BASE
+       ldr     x2, [x1, #CCI_MN_RNF_NODEID_LIST]
+       str     x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
+1:     ldr     x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
+       mvn     x0, x3
+       tst     x0, x3          /* Wait for domain addition to complete */
+       b.ne    1b
+
        /* Set the SMMU page size in the sACR register */
        ldr     x1, =SMMU_BASE
        ldr     w0, [x1, #0x10]

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 518e59c9634358fbb3cc39d16214b9d69b91b9b9..91214524117dd764ad257304cea6cb2c2a553de1 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -118,6 +118,12 @@
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x1400000000ULL
 #define CONFIG_SYS_PCIE4_PHYS_ADDR             0x1600000000ULL
 
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE            0x04000000
+#define CCI_MN_RNF_NODEID_LIST         0x180
+#define CCI_MN_DVM_DOMAIN_CTL          0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET      0x210
+
 #ifdef CONFIG_LS2085A
 #define CONFIG_MAX_CPUS                                16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8