armv8/ls1043: Add workaround for DDR erratum A-008850

Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 0cb010012e7add46e725741cbcb535e2bb9047f4..0fb5c7f0cc1770d7bddfdd8613a6847be4bead20 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -12,6 +12,8 @@
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr.h>
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
@@ -271,6 +273,39 @@ static void erratum_a009660(void)
 #endif
 }
 
+static void erratum_a008850_early(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+       /* part 1 of 2 */
+       struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+
+       /* disables propagation of barrier transactions to DDRC from CCI400 */
+       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+       /* disable the re-ordering in DDRC */
+       ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+#endif
+}
+
+void erratum_a008850_post(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
+       /* part 2 of 2 */
+       struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+       struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+       u32 tmp;
+
+       /* enable propagation of barrier transactions to DDRC from CCI400 */
+       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+       /* enable the re-ordering in DDRC */
+       tmp = ddr_in32(&ddr->eor);
+       tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
+       ddr_out32(&ddr->eor, tmp);
+#endif
+}
+
 void fsl_lsch2_early_init_f(void)
 {
        struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -295,6 +330,7 @@ void fsl_lsch2_early_init_f(void)
                 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
 
        /* Erratum */
+       erratum_a008850_early(); /* part 1 of 2 */
        erratum_a009929();
        erratum_a009660();
 }

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 10d17b2bef082b7fec3a4d8049f75ef8857957d3..a24dc2805d4a56079d30db878adade3880775950 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -191,6 +191,7 @@
 #define GICD_BASE              0x01401000
 #define GICC_BASE              0x01402000
 
+#define CONFIG_SYS_FSL_ERRATUM_A008850
 #define CONFIG_SYS_FSL_ERRATUM_A009663
 #define CONFIG_SYS_FSL_ERRATUM_A009929
 #define CONFIG_SYS_FSL_ERRATUM_A009942

diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c
index 3d3c53385a12c838b0229de1e03ca71e3e58a3c8..0fd835d74fb3712467719cb79b718740d06bf1ef 100644 (file)
--- a/board/freescale/ls1043aqds/ddr.c
+++ b/board/freescale/ls1043aqds/ddr.c
@@ -116,6 +116,7 @@ phys_size_t initdram(int board_type)
 
        dram_size = fsl_ddr_sdram();
 #endif
+       erratum_a008850_post();
 
 #ifdef CONFIG_FSL_DEEP_SLEEP
        fsl_dp_ddr_restore();

diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h
index 8adb660012596837e399af918085ea5926c9b0c2..d3f40822b7c5a0adce8f7c7d7eac01bd012bbbe9 100644 (file)
--- a/board/freescale/ls1043aqds/ddr.h
+++ b/board/freescale/ls1043aqds/ddr.h
@@ -7,6 +7,8 @@
 #ifndef __DDR_H__
 #define __DDR_H__
 
+extern void erratum_a008850_post(void);
+
 struct board_specific_parameters {
        u32 n_ranks;
        u32 datarate_mhz_high;

diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index fba6b8895155059737f1019815ee92a1b9642188..fc097d968a5b6d6770a12880f6d80dd9d6b4d205 100644 (file)
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -307,14 +307,6 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
-                                  CONFIG_SYS_CCI400_ADDR;
-
-       /* Set CCI-400 control override register to enable barrier
-        * transaction */
-       out_le32(&cci->ctrl_ord,
-                CCI400_CTRLORD_EN_BARRIER);
-
        select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
        board_retimer_init();
 

diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index 11bc0f24d9abe933f13ed335e4dc6a1d80c34008..1e2fd2ed0c136d25b8325fdd56dfb098e82de7ba 100644 (file)
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -177,6 +177,8 @@ phys_size_t initdram(int board_type)
 #else
        dram_size =  fsl_ddr_sdram_size();
 #endif
+       erratum_a008850_post();
+
 #ifdef CONFIG_FSL_DEEP_SLEEP
        fsl_dp_ddr_restore();
 #endif

diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h
index b17eb8088538b0f242d1182084c0450caae2c35e..8ca166b3ac93479b27d90e37dccd4d4b86fe8619 100644 (file)
--- a/board/freescale/ls1043ardb/ddr.h
+++ b/board/freescale/ls1043ardb/ddr.h
@@ -6,6 +6,9 @@
 
 #ifndef __DDR_H__
 #define __DDR_H__
+
+extern void erratum_a008850_post(void);
+
 struct board_specific_parameters {
        u32 n_ranks;
        u32 datarate_mhz_high;

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index ec5fdbfe27ec46ce8ac1b84a17db0b6a9a1d09c9..8d8013515a91cd1ed10e908e0791630dbaeb35f8 100644 (file)
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -83,14 +83,6 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-       struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
-
-       /*
-        * Set CCI-400 control override register to enable barrier
-        * transaction
-        */
-       out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
-
 #ifdef CONFIG_FSL_IFC
        init_final_memctl_regs();
 #endif

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index cf316a4665f4487a9a8d34e0809e9eab98dda345..44ae7fbb9cede2a17c90a95499c29e0bf6df9517 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -146,6 +146,10 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define WR_DATA_DELAY_SHIFT    10
 #endif
 
+/* DDR_EOR register */
+#define DDR_EOR_RD_REOD_DIS    0x07000000
+#define DDR_EOR_WD_REOD_DIS    0x00100000
+
 /* DDR_MD_CNTL */
 #define MD_CNTL_MD_EN          0x80000000
 #define MD_CNTL_CS_SEL_CS0     0x00000000