move L2 cache enable/disable function to cache.c in the omap3 SoC directory

Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
CC: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index 6fd07d0b7375fa01d4d192769777f63c89fd99c9..fcb5775a1c3be37a2d00ddc0b004beaee7813bb2 100644 (file)
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -33,12 +33,8 @@
 
 #include <common.h>
 #include <command.h>
-#include <asm/arch/sys_proto.h>
 #include <asm/system.h>
-
-#ifndef CONFIG_L2_OFF
-void l2cache_disable(void);
-#endif
+#include <asm/cache.h>
 
 static void cache_flush(void);
 
@@ -63,7 +59,7 @@ int cleanup_before_linux(void)
 
 #ifndef CONFIG_L2_OFF
        /* turn off L2 cache */
-       l2cache_disable();
+       l2_cache_disable();
        /* invalidate L2 cache also */
        v7_flush_dcache_all(get_device_type());
 #endif
@@ -72,72 +68,14 @@ int cleanup_before_linux(void)
        asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));
 
 #ifndef CONFIG_L2_OFF
-       l2cache_enable();
+       l2_cache_enable();
 #endif
 
        return 0;
 }
 
-void l2cache_enable()
-{
-       unsigned long i;
-       volatile unsigned int j;
-
-       /* ES2 onwards we can disable/enable L2 ourselves */
-       if (get_cpu_rev() >= CPU_3XX_ES20) {
-               __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-               __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
-               __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-       } else {
-               /* Save r0, r12 and restore them after usage */
-               __asm__ __volatile__("mov %0, r12":"=r"(j));
-               __asm__ __volatile__("mov %0, r0":"=r"(i));
-
-               /*
-                * GP Device ROM code API usage here
-                * r12 = AUXCR Write function and r0 value
-                */
-               __asm__ __volatile__("mov r12, #0x3");
-               __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-               __asm__ __volatile__("orr r0, r0, #0x2");
-               /* SMI instruction to call ROM Code API */
-               __asm__ __volatile__(".word 0xE1600070");
-               __asm__ __volatile__("mov r0, %0":"=r"(i));
-               __asm__ __volatile__("mov r12, %0":"=r"(j));
-       }
-
-}
-
-void l2cache_disable()
-{
-       unsigned long i;
-       volatile unsigned int j;
-
-       /* ES2 onwards we can disable/enable L2 ourselves */
-       if (get_cpu_rev() >= CPU_3XX_ES20) {
-               __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
-               __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
-               __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
-       } else {
-               /* Save r0, r12 and restore them after usage */
-               __asm__ __volatile__("mov %0, r12":"=r"(j));
-               __asm__ __volatile__("mov %0, r0":"=r"(i));
-
-               /*
-                * GP Device ROM code API usage here
-                * r12 = AUXCR Write function and r0 value
-                */
-               __asm__ __volatile__("mov r12, #0x3");
-               __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
-               __asm__ __volatile__("bic r0, r0, #0x2");
-               /* SMI instruction to call ROM Code API */
-               __asm__ __volatile__(".word 0xE1600070");
-               __asm__ __volatile__("mov r0, %0":"=r"(i));
-               __asm__ __volatile__("mov r12, %0":"=r"(j));
-       }
-}
-
 static void cache_flush(void)
 {
        asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
+

diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index 50176eeb35fc0551807f4ac00f07ecac9de21b33..1fbd0dcdac76dc0c4557bd9c707ed28e419dc0b0 100644 (file)
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -28,6 +28,7 @@ LIB   =  $(obj)lib$(SOC).a
 SOBJS  := lowlevel_init.o
 
 COBJS  += board.o
+COBJS  += cache.o
 COBJS  += clock.o
 COBJS  += gpio.o
 COBJS  += mem.o

diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 6e295994ab5dccd25b7991efd6b5f8f7a952f4c3..b665ec9eda9bc6f96a6110d2b0e5b6dbc9faa65a 100644 (file)
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -36,6 +36,7 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
+#include <asm/cache.h>
 
 extern omap3_sysinfo sysinfo;
 
@@ -206,9 +207,9 @@ void s_init(void)
 #endif
 
 #ifdef CONFIG_L2_OFF
-       l2cache_disable();
+       l2_cache_disable();
 #else
-       l2cache_enable();
+       l2_cache_enable();
 #endif
        /*
         * Writing to AuxCR in U-boot using SMI for GP DEV

diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c
new file mode 100644 (file)
index 0000000..f49ed4a
--- /dev/null
+++ b/cpu/arm_cortexa8/omap3/cache.c
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2008 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * omap3 L2 cache code
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/cache.h>
+
+void l2_cache_enable(void)
+{
+       unsigned long i;
+       volatile unsigned int j;
+
+       /* ES2 onwards we can disable/enable L2 ourselves */
+       if (get_cpu_rev() >= CPU_3XX_ES20) {
+               __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+               __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
+               __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+       } else {
+               /* Save r0, r12 and restore them after usage */
+               __asm__ __volatile__("mov %0, r12":"=r"(j));
+               __asm__ __volatile__("mov %0, r0":"=r"(i));
+
+               /*
+                * GP Device ROM code API usage here
+                * r12 = AUXCR Write function and r0 value
+                */
+               __asm__ __volatile__("mov r12, #0x3");
+               __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+               __asm__ __volatile__("orr r0, r0, #0x2");
+               /* SMI instruction to call ROM Code API */
+               __asm__ __volatile__(".word 0xE1600070");
+               __asm__ __volatile__("mov r0, %0":"=r"(i));
+               __asm__ __volatile__("mov r12, %0":"=r"(j));
+       }
+
+}
+
+void l2_cache_disable(void)
+{
+       unsigned long i;
+       volatile unsigned int j;
+
+       /* ES2 onwards we can disable/enable L2 ourselves */
+       if (get_cpu_rev() >= CPU_3XX_ES20) {
+               __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+               __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
+               __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+       } else {
+               /* Save r0, r12 and restore them after usage */
+               __asm__ __volatile__("mov %0, r12":"=r"(j));
+               __asm__ __volatile__("mov %0, r0":"=r"(i));
+
+               /*
+                * GP Device ROM code API usage here
+                * r12 = AUXCR Write function and r0 value
+                */
+               __asm__ __volatile__("mov r12, #0x3");
+               __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
+               __asm__ __volatile__("bic r0, r0, #0x2");
+               /* SMI instruction to call ROM Code API */
+               __asm__ __volatile__(".word 0xE1600070");
+               __asm__ __volatile__("mov r0, %0":"=r"(i));
+               __asm__ __volatile__("mov r12, %0":"=r"(j));
+       }
+}
+

diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h
index 248240bef0ab18d174e44bc436f66c83a9ab59cb..d0518be28cac90da47e0dd89fd28e6419cd6f777 100644 (file)
--- a/include/asm-arm/cache.h
+++ b/include/asm-arm/cache.h
@@ -38,4 +38,8 @@ static inline void invalidate_l2_cache(void)
                : : "r" (val) : "cc");
        isb();
 }
+
+void l2_cache_enable(void);
+void l2_cache_disable(void);
+
 #endif /* _ASM_CACHE_H */