]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
arm: dts: imx8mn: Sync with linux-next 20231019
authorFabio Estevam <festevam@denx.de>
Thu, 19 Oct 2023 12:06:22 +0000 (09:06 -0300)
committerFabio Estevam <festevam@gmail.com>
Wed, 13 Dec 2023 12:52:18 +0000 (09:52 -0300)
Sync imx8mn.dtsi with linux-next 20231019.

Signed-off-by: Fabio Estevam <festevam@denx.de>
arch/arm/dts/imx8mn.dtsi

index cb2836bfbd95c7a3d7d354a6b63bea2e885f5925..1bb1d0c1bae4de28bcb2939a54b353efcbc2144e 100644 (file)
                A53_L2: l2-cache0 {
                        compatible = "cache";
                        cache-level = <2>;
+                       cache-unified;
                        cache-size = <0x80000>;
                        cache-line-size = <64>;
                        cache-sets = <512>;
                                sai2: sai@30020000 {
                                        compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
                                        reg = <0x30020000 0x10000>;
+                                       #sound-dai-cells = <0>;
                                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
                                                <&clk IMX8MN_CLK_DUMMY>,
                                sai3: sai@30030000 {
                                        compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
                                        reg = <0x30030000 0x10000>;
+                                       #sound-dai-cells = <0>;
                                        interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
                                                 <&clk IMX8MN_CLK_DUMMY>,
                                sai5: sai@30050000 {
                                        compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
                                        reg = <0x30050000 0x10000>;
+                                       #sound-dai-cells = <0>;
                                        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
                                                 <&clk IMX8MN_CLK_DUMMY>,
                                sai6: sai@30060000 {
                                        compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
                                        reg = <0x30060000  0x10000>;
+                                       #sound-dai-cells = <0>;
                                        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
                                                 <&clk IMX8MN_CLK_DUMMY>,
                                                      "pll8k", "pll11k", "clkext3";
                                        dmas = <&sdma2 24 25 0x80000000>;
                                        dma-names = "rx";
+                                       #sound-dai-cells = <0>;
                                        status = "disabled";
                                };
 
                                sai7: sai@300b0000 {
                                        compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
                                        reg = <0x300b0000 0x10000>;
+                                       #sound-dai-cells = <0>;
                                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                                        clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
                                                 <&clk IMX8MN_CLK_DUMMY>,
                                compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
                                reg = <0x30260000 0x10000>;
                                clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
+                               nvmem-cells = <&tmu_calib>;
+                               nvmem-cell-names = "calib";
                                #thermal-sensor-cells = <0>;
                        };
 
                                reg = <0x30330000 0x10000>;
                        };
 
-                       gpr: iomuxc-gpr@30340000 {
+                       gpr: syscon@30340000 {
                                compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
                                reg = <0x30340000 0x10000>;
                        };
                                #address-cells = <1>;
                                #size-cells = <1>;
 
-                               imx8mn_uid: unique-id@410 {
+                               /*
+                                * The register address below maps to the MX8M
+                                * Fusemap Description Table entries this way.
+                                * Assuming
+                                *   reg = <ADDR SIZE>;
+                                * then
+                                *   Fuse Address = (ADDR * 4) + 0x400
+                                * Note that if SIZE is greater than 4, then
+                                * each subsequent fuse is located at offset
+                                * +0x10 in Fusemap Description Table (e.g.
+                                * reg = <0x4 0x8> describes fuses 0x410 and
+                                * 0x420).
+                                */
+                               imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
                                        reg = <0x4 0x8>;
                                };
 
-                               cpu_speed_grade: speed-grade@10 {
+                               cpu_speed_grade: speed-grade@10 { /* 0x440 */
                                        reg = <0x10 4>;
                                };
 
-                               fec_mac_address: mac-address@90 {
+                               tmu_calib: calib@3c { /* 0x4f0 */
+                                       reg = <0x3c 4>;
+                               };
+
+                               fec_mac_address: mac-address@90 { /* 0x640 */
                                        reg = <0x90 6>;
                                };
                        };
 
-                       anatop: anatop@30360000 {
-                               compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
-                                            "syscon";
+                       anatop: clock-controller@30360000 {
+                               compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
                                reg = <0x30360000 0x10000>;
+                               #clock-cells = <1>;
                        };
 
                        snvs: snvs@30370000 {
                                        pgc_otg1: power-domain@1 {
                                                #power-domain-cells = <0>;
                                                reg = <IMX8MN_POWER_DOMAIN_OTG1>;
-                                               power-domains = <&pgc_hsiomix>;
                                        };
 
                                        pgc_gpumix: power-domain@2 {
                        #size-cells = <1>;
                        ranges;
 
+                       lcdif: lcdif@32e00000 {
+                               compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
+                               reg = <0x32e00000 0x10000>;
+                               clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
+                               clock-names = "pix", "axi", "disp_axi";
+                               interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
+                               status = "disabled";
+
+                               port {
+                                       lcdif_to_dsim: endpoint {
+                                               remote-endpoint = <&dsim_from_lcdif>;
+                                       };
+                               };
+                       };
+
+                       mipi_dsi: dsi@32e10000 {
+                               compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
+                               reg = <0x32e10000 0x400>;
+                               clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+                                        <&clk IMX8MN_CLK_DSI_PHY_REF>;
+                               clock-names = "bus_clk", "sclk_mipi";
+                               interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                               power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+
+                                               dsim_from_lcdif: endpoint {
+                                                       remote-endpoint = <&lcdif_to_dsim>;
+                                               };
+                                       };
+                               };
+                       };
+
+                       isi: isi@32e20000 {
+                               compatible = "fsl,imx8mn-isi";
+                               reg = <0x32e20000 0x8000>;
+                               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+                                        <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+                               clock-names = "axi", "apb";
+                               fsl,blk-ctrl = <&disp_blk_ctrl>;
+                               power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               isi_in: endpoint {
+                                                       remote-endpoint = <&mipi_csi_out>;
+                                               };
+                                       };
+                               };
+                       };
+
                        disp_blk_ctrl: blk-ctrl@32e28000 {
                                compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
                                reg = <0x32e28000 0x100>;
                                              "lcdif-axi", "lcdif-apb", "lcdif-pix",
                                              "dsi-pclk", "dsi-ref",
                                              "csi-aclk", "csi-pclk";
+                               assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
+                                                 <&clk IMX8MN_CLK_DSI_PHY_REF>,
+                                                 <&clk IMX8MN_CLK_DISP_PIXEL>,
+                                                 <&clk IMX8MN_CLK_DISP_AXI>,
+                                                 <&clk IMX8MN_CLK_DISP_APB>;
+                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
+                                                        <&clk IMX8MN_CLK_24M>,
+                                                        <&clk IMX8MN_VIDEO_PLL1_OUT>,
+                                                        <&clk IMX8MN_SYS_PLL2_1000M>,
+                                                        <&clk IMX8MN_SYS_PLL1_800M>;
+                               assigned-clock-rates = <266000000>,
+                                                      <24000000>,
+                                                      <594000000>,
+                                                      <500000000>,
+                                                      <200000000>;
                                #power-domain-cells = <1>;
                        };
 
+                       mipi_csi: mipi-csi@32e30000 {
+                               compatible = "fsl,imx8mm-mipi-csi2";
+                               reg = <0x32e30000 0x1000>;
+                               interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                               assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
+                               assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
+                               assigned-clock-rates = <333000000>;
+                               clock-frequency = <333000000>;
+                               clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+                                        <&clk IMX8MN_CLK_CAMERA_PIXEL>,
+                                        <&clk IMX8MN_CLK_CSI1_PHY_REF>,
+                                        <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
+                               clock-names = "pclk", "wrap", "phy", "axi";
+                               power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+
+                                               mipi_csi_out: endpoint {
+                                                       remote-endpoint = <&isi_in>;
+                                               };
+                                       };
+                               };
+                       };
+
                        usbotg1: usb@32e40000 {
-                               compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
+                               compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
                                reg = <0x32e40000 0x200>;
                                interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
                                assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
                                phys = <&usbphynop1>;
                                fsl,usbmisc = <&usbmisc1 0>;
-                               power-domains = <&pgc_otg1>;
+                               power-domains = <&pgc_hsiomix>;
                                status = "disabled";
                        };
 
                        usbmisc1: usbmisc@32e40200 {
-                               compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
+                               compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",
+                                            "fsl,imx6q-usbmisc";
                                #index-cells = <1>;
                                reg = <0x32e40200 0x200>;
                        };
                                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
                        #dma-cells = <1>;
                        dma-channels = <4>;
                        clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
                gpmi: nand-controller@33002000 {
                        compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
                        #address-cells = <1>;
-                       #size-cells = <1>;
+                       #size-cells = <0>;
                        reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
                        reg-names = "gpmi-nand", "bch";
                        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
                assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
                clock-names = "main_clk";
+               power-domains = <&pgc_otg1>;
        };
 };