x86: quark: Implement PIRQ routing

Intel Quark SoC has the same interrupt routing mechanism as the
Queensbay platform, only the difference is that PCI devices'
INTA/B/C/D are harcoded and cannot be changed freely.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index e78a271c5090935acbfeb0d684e3afcd34b085d9..20cc09e113d9d568ab92306a09b07953499b0cef 100644 (file)
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -9,6 +9,7 @@
 #include <netdev.h>
 #include <phy.h>
 #include <asm/io.h>
+#include <asm/irq.h>
 #include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>
@@ -147,3 +148,33 @@ int cpu_eth_init(bd_t *bis)
        else
                return 0;
 }
+
+void cpu_irq_init(void)
+{
+       struct quark_rcba *rcba;
+       u32 base;
+
+       base = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, LB_RCBA);
+       base &= ~MEM_BAR_EN;
+       rcba = (struct quark_rcba *)base;
+
+       /*
+        * Route Quark PCI device interrupt pin to PIRQ
+        *
+        * Route device#23's INTA/B/C/D to PIRQA/B/C/D
+        * Route device#20,21's INTA/B/C/D to PIRQE/F/G/H
+        */
+       writew(PIRQC, &rcba->rmu_ir);
+       writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12),
+              &rcba->d23_ir);
+       writew(PIRQD, &rcba->core_ir);
+       writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12),
+              &rcba->d20d21_ir);
+}
+
+int arch_misc_init(void)
+{
+       pirq_init();
+
+       return 0;
+}

diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index 60dbc5f8a30c657dcb112fb56faf22ed46e718cf..2ba081e9dc22bf60ed4d72c4958e67a596326ca2 100644 (file)
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <dt-bindings/mrc/quark.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
 
 /include/ "skeleton.dtsi"
 
@@ -67,6 +68,27 @@
                        clock-frequency = <44236800>;
                        current-speed = <115200>;
                };
+
+               irq-router@1f,0 {
+                       reg = <0x0000f800 0 0 0 0>;
+                       compatible = "intel,irq-router";
+                       intel,pirq-config = "pci";
+                       intel,pirq-link = <0x60 8>;
+                       intel,pirq-mask = <0xdef8>;
+                       intel,pirq-routing = <
+                               PCI_BDF(0, 20, 0) INTA PIRQE
+                               PCI_BDF(0, 20, 1) INTB PIRQF
+                               PCI_BDF(0, 20, 2) INTC PIRQG
+                               PCI_BDF(0, 20, 3) INTD PIRQH
+                               PCI_BDF(0, 20, 4) INTA PIRQE
+                               PCI_BDF(0, 20, 5) INTB PIRQF
+                               PCI_BDF(0, 20, 6) INTC PIRQG
+                               PCI_BDF(0, 20, 7) INTD PIRQH
+                               PCI_BDF(0, 21, 0) INTA PIRQE
+                               PCI_BDF(0, 21, 1) INTB PIRQF
+                               PCI_BDF(0, 21, 2) INTC PIRQG
+                       >;
+               };
        };
 
        gpioa {

diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h
index 4af3dedc9579bd97613c1ce4ee4e2e44c11fc9b6..7882f339f0aa849511ffa082de1a495c85ef63ea 100644 (file)
--- a/arch/x86/include/asm/arch-quark/device.h
+++ b/arch/x86/include/asm/arch-quark/device.h
@@ -9,20 +9,60 @@
 
 #include <pci.h>
 
-#define QUARK_HOST_BRIDGE      PCI_BDF(0, 0, 0)
-#define QUARK_MMC_SDIO         PCI_BDF(0, 20, 0)
-#define QUARK_UART0            PCI_BDF(0, 20, 1)
-#define QUARK_USB_DEVICE       PCI_BDF(0, 20, 2)
-#define QUARK_USB_EHCI         PCI_BDF(0, 20, 3)
-#define QUARK_USB_OHCI         PCI_BDF(0, 20, 4)
-#define QUARK_UART1            PCI_BDF(0, 20, 5)
-#define QUARK_EMAC0            PCI_BDF(0, 20, 6)
-#define QUARK_EMAC1            PCI_BDF(0, 20, 7)
-#define QUARK_SPI0             PCI_BDF(0, 21, 0)
-#define QUARK_SPI1             PCI_BDF(0, 21, 1)
-#define QUARK_I2C_GPIO         PCI_BDF(0, 21, 2)
-#define QUARK_PCIE0            PCI_BDF(0, 23, 0)
-#define QUARK_PCIE1            PCI_BDF(0, 23, 1)
-#define QUARK_LEGACY_BRIDGE    PCI_BDF(0, 31, 0)
+#define QUARK_HOST_BRIDGE_DEV  0
+#define QUARK_HOST_BRIDGE_FUNC 0
+
+#define QUARK_DEV_20           20
+#define QUARK_MMC_SDIO_FUNC    0
+#define QUARK_UART0_FUNC       1
+#define QUARK_USB_DEVICE_FUNC  2
+#define QUARK_USB_EHCI_FUNC    3
+#define QUARK_USB_OHCI_FUNC    4
+#define QUARK_UART1_FUNC       5
+#define QUARK_EMAC0_FUNC       6
+#define QUARK_EMAC1_FUNC       7
+
+#define QUARK_DEV_21           21
+#define QUARK_SPI0_FUNC                0
+#define QUARK_SPI1_FUNC                1
+#define QUARK_I2C_GPIO_FUNC    2
+
+#define QUARK_DEV_23           23
+#define QUARK_PCIE0_FUNC       0
+#define QUARK_PCIE1_FUNC       1
+
+#define QUARK_LGC_BRIDGE_DEV   31
+#define QUARK_LGC_BRIDGE_FUNC  0
+
+#define QUARK_HOST_BRIDGE      \
+       PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
+#define QUARK_MMC_SDIO         \
+       PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC)
+#define QUARK_UART0            \
+       PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC)
+#define QUARK_USB_DEVICE       \
+       PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC)
+#define QUARK_USB_EHCI         \
+       PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC)
+#define QUARK_USB_OHCI         \
+       PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC)
+#define QUARK_UART1            \
+       PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC)
+#define QUARK_EMAC0            \
+       PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC)
+#define QUARK_EMAC1            \
+       PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC)
+#define QUARK_SPI0             \
+       PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC)
+#define QUARK_SPI1             \
+       PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC)
+#define QUARK_I2C_GPIO         \
+       PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC)
+#define QUARK_PCIE0            \
+       PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC)
+#define QUARK_PCIE1            \
+       PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
+#define QUARK_LEGACY_BRIDGE    \
+       PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
 
 #endif /* _QUARK_DEVICE_H_ */

diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
index 6dd02fd31edac51174ce9e4474c63b5ff1bd25cb..c9979280b625a9ebe3ff5c7236a332dc352c0b10 100644 (file)
--- a/arch/x86/include/asm/arch-quark/quark.h
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -76,4 +76,19 @@
 #define LB_BC                  0xd8
 #define LB_RCBA                        0xf0
 
+#ifndef __ASSEMBLY__
+
+/* Root Complex Register Block */
+struct quark_rcba {
+       u32     rctl;
+       u32     esd;
+       u32     rsvd1[3150];
+       u16     rmu_ir;
+       u16     d23_ir;
+       u16     core_ir;
+       u16     d20d21_ir;
+};
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* _QUARK_H_ */

diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index c0a937f91e73fe4e0902b4fd76931925d9d708b3..a3b564ec54fb6e418829e8926d7e8e5079f1258d 100644 (file)
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -6,3 +6,4 @@ CONFIG_TARGET_GALILEO=y
 CONFIG_CMD_NET=y
 CONFIG_OF_CONTROL=y
 CONFIG_ETH_DESIGNWARE=y
+CONFIG_GENERATE_PIRQ_TABLE=y

diff --git a/include/configs/galileo.h b/include/configs/galileo.h
index 083d8b41051d22d630d1f71dee7926723232130b..fd89bf30ef3a3d87547cf3437113e4618d89ab1f 100644 (file)
--- a/include/configs/galileo.h
+++ b/include/configs/galileo.h
@@ -15,6 +15,7 @@
 
 #define CONFIG_SYS_MONITOR_LEN         (1 << 20)
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ARCH_MISC_INIT
 
 #define CONFIG_X86_SERIAL