spi: zynq_qspi: Add configuration to disable LQSPI feature

When the Zynq Boot ROM code loads the payload from QSPI it uses the
LQSPI feature of the QSPI device, however it does not clean up its
configuration before handing over to the payload which leaves the device
confgured to by-pass the standard non-linear operating mode.

This ensures the Linear QSPI mode is disabled before re-enabling the
device.

Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/drivers/spi/zynq_qspi.c b/drivers/spi/zynq_qspi.c
index 5825c6d8f1f8fce6c015acfe79225c87a3054395..b98663c23b21e72e62eb970c42ed1f68b7135d42 100644 (file)
--- a/drivers/spi/zynq_qspi.c
+++ b/drivers/spi/zynq_qspi.c
@@ -30,6 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define ZYNQ_QSPI_IXR_TXOW_MASK                BIT(2)  /* TX_FIFO_not_full */
 #define ZYNQ_QSPI_IXR_ALL_MASK         GENMASK(6, 0)   /* All IXR bits */
 #define ZYNQ_QSPI_ENR_SPI_EN_MASK      BIT(0)  /* SPI Enable */
+#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
 
 /* zynq qspi Transmit Data Register */
 #define ZYNQ_QSPI_TXD_00_00_OFFSET     0x1C    /* Transmit 4-byte inst */
@@ -68,6 +69,9 @@ struct zynq_qspi_regs {
        u32 txd1r;      /* 0x80 */
        u32 txd2r;      /* 0x84 */
        u32 txd3r;      /* 0x88 */
+       u32 reserved1[5];
+       u32 lqspicfg;   /* 0xA0 */
+       u32 lqspists;   /* 0xA4 */
 };
 
 /* zynq qspi platform data */
@@ -143,6 +147,11 @@ static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
                ZYNQ_QSPI_CR_MSTREN_MASK;
        writel(confr, &regs->cr);
 
+       /* Disable the LQSPI feature */
+       confr = readl(&regs->lqspicfg);
+       confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
+       writel(confr, &regs->lqspicfg);
+
        /* Enable SPI */
        writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
 }