riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit

All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0917b831083a7eae5a7091792e2c9e2f00643756..70576846f2430d2ca84adefcdf48a12794327277 100644 (file)
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -135,7 +135,7 @@
 
                plic0: interrupt-controller@e4000000 {
                        compatible = "riscv,plic0";
-                       #interrupt-cells = <1>;
+                       #interrupt-cells = <2>;
                        interrupt-controller;
                        reg = <0xe4000000 0x2000000>;
                        riscv,ndev=<71>;