Blackfin: minimize time cache is turned off when replacing cplb entries

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c
index d17c0a195dcfed6aed122b0ddb7022d695fc7fc6..e72b347a6346ea604fe4432230080f7e72a2c8b4 100644 (file)
--- a/cpu/blackfin/traps.c
+++ b/cpu/blackfin/traps.c
@@ -117,17 +117,6 @@ void trap_c(struct pt_regs *regs)
                        debug("CPLB addr %p matches map 0x%p - 0x%p\n", new_cplb_addr, bfin_memory_map[i].start, bfin_memory_map[i].end);
                new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
 
-               /* Turn the cache off */
-               SSYNC();
-               if (data) {
-                       asm(" .align 8; ");
-                       *pDMEM_CONTROL &= ~ENDCPLB;
-               } else {
-                       asm(" .align 8; ");
-                       *pIMEM_CONTROL &= ~ENICPLB;
-               }
-               SSYNC();
-
                if (data) {
                        CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
                        CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
@@ -149,8 +138,17 @@ void trap_c(struct pt_regs *regs)
 
                debug("evicting entry %i: 0x%p 0x%08X\n", i, *CPLB_ADDR, *CPLB_DATA);
                last_evicted = i + 1;
+
+               /* need to turn off cplbs whenever we muck with the cplb table */
+#if ENDCPLB != ENICPLB
+# error cplb enable bit violates my sanity
+#endif
+               uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
+               bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
                *CPLB_ADDR = new_cplb_addr;
                *CPLB_DATA = new_cplb_data;
+               bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
+               SSYNC();
 
                /* dump current table for debugging purposes */
                CPLB_ADDR = CPLB_ADDR_BASE;
@@ -158,17 +156,6 @@ void trap_c(struct pt_regs *regs)
                for (i = 0; i < 16; ++i)
                        debug("%2i 0x%p 0x%08X\n", i, *CPLB_ADDR++, *CPLB_DATA++);
 
-               /* Turn the cache back on */
-               SSYNC();
-               if (data) {
-                       asm(" .align 8; ");
-                       *pDMEM_CONTROL |= ENDCPLB;
-               } else {
-                       asm(" .align 8; ");
-                       *pIMEM_CONTROL |= ENICPLB;
-               }
-               SSYNC();
-
                break;
        }