x86: fsp: Don't program MTRR for DRAM for FSP1

There are several outstanding issues as to why this does not apply
to FSP1:

* For FSP1, the system memory and reserved memory used by FSP are
  already programmed in the MTRR by FSP.
* The 'mtrr_top' mistakenly includes TSEG memory range that has the
  same RES_MEM_RESERVED resource type. Its address is programmed
  and reported by FSP to be near the top of 4 GiB space, which is
  not what we want for SDRAM.
* The call to mtrr_add_request() is not guaranteed to have its size
  to be exactly the power of 2. This causes reserved bits of the
  IA32_MTRR_PHYSMASK register to be written which generates #GP.

For FSP2, it seems this is necessary as without this, U-Boot boot
process on Chromebook Coral goes very slowly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested on chromebook_coral, chromebook_samus, chromebook_link, minnowmax
Tested-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 8ad9aeedac0e6c9c3a81d2999fb2b29cc04214ca..2bd408d0c5670e73cb9239786ceeb74282eac4b8 100644 (file)
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -48,12 +48,28 @@ int dram_init_banksize(void)
        phys_addr_t mtrr_top;
        phys_addr_t low_end;
        uint bank;
+       bool update_mtrr;
+
+       /*
+        * For FSP1, the system memory and reserved memory used by FSP are
+        * already programmed in the MTRR by FSP. Also it is observed that
+        * FSP on Intel Queensbay platform reports the TSEG memory range
+        * that has the same RES_MEM_RESERVED resource type whose address
+        * is programmed by FSP to be near the top of 4 GiB space, which is
+        * not what we want for DRAM.
+        *
+        * However it seems FSP2's behavior is different. We need to add the
+        * DRAM range in MTRR otherwise the boot process goes very slowly,
+        * which was observed on Chrromebook Coral with FSP2.
+        */
+       update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2);
 
        if (!ll_boot_init()) {
                gd->bd->bi_dram[0].start = 0;
                gd->bd->bi_dram[0].size = gd->ram_size;
 
-               mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
+               if (update_mtrr)
+                       mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size);
                return 0;
        }
 
@@ -76,8 +92,10 @@ int dram_init_banksize(void)
                } else {
                        gd->bd->bi_dram[bank].start = res_desc->phys_start;
                        gd->bd->bi_dram[bank].size = res_desc->len;
-                       mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
-                                        res_desc->len);
+                       if (update_mtrr)
+                               mtrr_add_request(MTRR_TYPE_WRBACK,
+                                                res_desc->phys_start,
+                                                res_desc->len);
                        log_debug("ram %llx %llx\n",
                                  gd->bd->bi_dram[bank].start,
                                  gd->bd->bi_dram[bank].size);
@@ -92,7 +110,8 @@ int dram_init_banksize(void)
         * Set up an MTRR to the top of low, reserved memory. This is necessary
         * for graphics to run at full speed in U-Boot.
         */
-       mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
+       if (update_mtrr)
+               mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
 
        return 0;
 }