SPI configuration items (port pins to use, etc). For
an example, see include/configs/sacsng.h.
-- FPGA Support: CONFIG_FPGA_COUNT
+- FPGA Support: CONFIG_FPGA
- Specify the number of FPGA devices to support.
+ Enables FPGA subsystem.
+
+ CONFIG_FPGA_<vendor>
+
+ Enables support for specific chip vendors.
+ (ALTERA, XILINX)
- CONFIG_FPGA
+ CONFIG_FPGA_<family>
- Used to specify the types of FPGA devices. For example,
- #define CONFIG_FPGA CFG_XILINX_VIRTEX2
+ Enables support for FPGA family.
+ (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
+
+ CONFIG_FPGA_COUNT
+
+ Specify the number of FPGA devices to support.
CFG_FPGA_PROG_FEEDBACK
DECLARE_GLOBAL_DATA_PTR;
-#if (CONFIG_FPGA)
+#if defined(CONFIG_FPGA)
#if 0
#define GEN860T_FPGA_DEBUG
mii_init ();
#endif
-#if (CONFIG_FPGA)
+#if defined(CONFIG_FPGA)
gen860t_init_fpga ();
#endif
return 0;
#include <common.h> /* core U-Boot definitions */
#include <ACEX1K.h> /* ACEX device family */
-#if (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_ACEX1K)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
}
-#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_ACEX1K)) */
+#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_ACEX1K */
#define PRINTF(fmt,args...)
#endif
-#if (CONFIG_FPGA & CFG_FPGA_ALTERA)
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
/* Local Static Functions */
static int altera_validate (Altera_desc * desc, char *fn);
switch (desc->family) {
case Altera_ACEX1K:
case Altera_CYC2:
-#if (CONFIG_FPGA & CFG_ACEX1K)
+#if defined(CONFIG_FPGA_ACEX1K)
PRINTF ("%s: Launching the ACEX1K Loader...\n",
__FUNCTION__);
ret_val = ACEX1K_load (desc, buf, bsize);
-#elif (CONFIG_FPGA & CFG_CYCLON2)
+#elif defined CONFIG_FPGA_CYCLON2
PRINTF ("%s: Launching the CYCLON II Loader...\n",
__FUNCTION__);
ret_val = CYC2_load (desc, buf, bsize);
} else {
switch (desc->family) {
case Altera_ACEX1K:
-#if (CONFIG_FPGA & CFG_ACEX)
+#if defined(CONFIG_FPGA_ACEX)
PRINTF ("%s: Launching the ACEX1K Reader...\n",
__FUNCTION__);
ret_val = ACEX1K_dump (desc, buf, bsize);
switch (desc->family) {
case Altera_ACEX1K:
case Altera_CYC2:
-#if (CONFIG_FPGA & CFG_ACEX1K)
+#if defined(CONFIG_FPGA_ACEX1K)
ACEX1K_info (desc);
-#elif (CONFIG_FPGA & CFG_CYCLON2)
+#elif defined(CONFIG_FPGA_CYCLON2)
CYC2_info (desc);
#else
/* just in case */
} else {
switch (desc->family) {
case Altera_ACEX1K:
-#if (CONFIG_FPGA & CFG_ACEX1K)
+#if defined(CONFIG_FPGA_ACEX1K)
ret_val = ACEX1K_reloc (desc, reloc_offset);
#else
printf ("%s: No support for ACEX devices.\n",
#endif
break;
case Altera_CYC2:
-#if (CONFIG_FPGA & CFG_CYCLON2)
+#if defined(CONFIG_FPGA_CYCLON2)
ret_val = CYC2_reloc (desc, reloc_offset);
#else
printf ("%s: No support for CYCLON II devices.\n",
/* ------------------------------------------------------------------------- */
-#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */
+#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */
/* Convert bitstream data and load into the fpga */
int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
{
-#if (CONFIG_FPGA & CFG_FPGA_XILINX)
+#if defined(CONFIG_FPGA_XILINX)
unsigned int length;
unsigned char* swapdata;
unsigned int swapsize;
#include <altera.h>
#include <ACEX1K.h> /* ACEX device family */
-#if (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA) && defined(CONFIG_FPGA_CYCLON2)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
return ret_val;
}
-#endif /* (CONFIG_FPGA & (CFG_ALTERA | CFG_CYCLON2)) */
+#endif /* CONFIG_FPGA && CONFIG_FPGA_ALTERA && CONFIG_FPGA_CYCLON2 */
static void fpga_no_sup( char *fn, char *msg )
{
if ( fn && msg ) {
- printf( "%s: No support for %s. CONFIG_FPGA defined as 0x%x.\n",
- fn, msg, CONFIG_FPGA );
+ printf( "%s: No support for %s.\n", fn, msg);
} else if ( msg ) {
- printf( "No support for %s. CONFIG_FPGA defined as 0x%x.\n",
- msg, CONFIG_FPGA );
+ printf( "No support for %s.\n", msg);
} else {
- printf( "No FPGA suport! CONFIG_FPGA defined as 0x%x.\n",
- CONFIG_FPGA );
+ printf( "No FPGA suport!\n");
}
}
printf( "%s: Null buffer.\n", fn );
return (fpga_desc * const)NULL;
}
- if ( !bsize ) {
- printf( "%s: Null buffer size.\n", fn );
- return (fpga_desc * const)NULL;
- }
-
return desc;
}
switch ( desc->devtype ) {
case fpga_xilinx:
-#if CONFIG_FPGA & CFG_FPGA_XILINX
+#if defined(CONFIG_FPGA_XILINX)
printf( "Xilinx Device\nDescriptor @ 0x%p\n", desc );
ret_val = xilinx_info( desc->devdesc );
#else
#endif
break;
case fpga_altera:
-#if CONFIG_FPGA & CFG_FPGA_ALTERA
+#if defined(CONFIG_FPGA_ALTERA)
printf( "Altera Device\nDescriptor @ 0x%p\n", desc );
ret_val = altera_info( desc->devdesc );
#else
switch ( devtype ) {
case fpga_xilinx:
-#if CONFIG_FPGA & CFG_FPGA_XILINX
+#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_reloc( desc, reloc_off );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
-#if CONFIG_FPGA & CFG_FPGA_ALTERA
+#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_reloc( desc, reloc_off );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
if ( desc ) {
switch ( desc->devtype ) {
case fpga_xilinx:
-#if CONFIG_FPGA & CFG_FPGA_XILINX
+#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_load( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
-#if CONFIG_FPGA & CFG_FPGA_ALTERA
+#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_load( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
if ( desc ) {
switch ( desc->devtype ) {
case fpga_xilinx:
-#if CONFIG_FPGA & CFG_FPGA_XILINX
+#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_dump( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" );
#endif
break;
case fpga_altera:
-#if CONFIG_FPGA & CFG_FPGA_ALTERA
+#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_dump( desc->devdesc, buf, bsize );
#else
fpga_no_sup( (char *)__FUNCTION__, "Altera devices" );
#include <common.h> /* core U-Boot definitions */
#include <spartan2.h> /* Spartan-II device family */
-#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN2))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN2)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#include <common.h> /* core U-Boot definitions */
#include <spartan3.h> /* Spartan-II device family */
-#if (CONFIG_FPGA & (CFG_XILINX | CFG_SPARTAN3))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN3)
/* Define FPGA_DEBUG to get debug printf's */
#ifdef FPGA_DEBUG
#include <common.h>
#include <virtex2.h>
-#if (CONFIG_FPGA & (CFG_XILINX | CFG_VIRTEX2))
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_VIRTEX2)
#if 0
#define FPGA_DEBUG
#include <spartan2.h>
#include <spartan3.h>
-#if (CONFIG_FPGA & CFG_FPGA_XILINX)
+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
#if 0
#define FPGA_DEBUG
} else
switch (desc->family) {
case Xilinx_Spartan2:
-#if (CONFIG_FPGA & CFG_SPARTAN2)
+#if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Loader...\n",
__FUNCTION__);
ret_val = Spartan2_load (desc, buf, bsize);
#endif
break;
case Xilinx_Spartan3:
-#if (CONFIG_FPGA & CFG_SPARTAN3)
+#if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Loader...\n",
__FUNCTION__);
ret_val = Spartan3_load (desc, buf, bsize);
#endif
break;
case Xilinx_Virtex2:
-#if (CONFIG_FPGA & CFG_VIRTEX2)
+#if defined(CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Loader...\n",
__FUNCTION__);
ret_val = Virtex2_load (desc, buf, bsize);
} else
switch (desc->family) {
case Xilinx_Spartan2:
-#if (CONFIG_FPGA & CFG_SPARTAN2)
+#if defined(CONFIG_FPGA_SPARTAN2)
PRINTF ("%s: Launching the Spartan-II Reader...\n",
__FUNCTION__);
ret_val = Spartan2_dump (desc, buf, bsize);
#endif
break;
case Xilinx_Spartan3:
-#if (CONFIG_FPGA & CFG_SPARTAN3)
+#if defined(CONFIG_FPGA_SPARTAN3)
PRINTF ("%s: Launching the Spartan-III Reader...\n",
__FUNCTION__);
ret_val = Spartan3_dump (desc, buf, bsize);
#endif
break;
case Xilinx_Virtex2:
-#if (CONFIG_FPGA & CFG_VIRTEX2)
+#if defined( CONFIG_FPGA_VIRTEX2)
PRINTF ("%s: Launching the Virtex-II Reader...\n",
__FUNCTION__);
ret_val = Virtex2_dump (desc, buf, bsize);
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
switch (desc->family) {
case Xilinx_Spartan2:
-#if (CONFIG_FPGA & CFG_SPARTAN2)
+#if defined(CONFIG_FPGA_SPARTAN2)
Spartan2_info (desc);
#else
/* just in case */
#endif
break;
case Xilinx_Spartan3:
-#if (CONFIG_FPGA & CFG_SPARTAN3)
+#if defined(CONFIG_FPGA_SPARTAN3)
Spartan3_info (desc);
#else
/* just in case */
#endif
break;
case Xilinx_Virtex2:
-#if (CONFIG_FPGA & CFG_VIRTEX2)
+#if defined(CONFIG_FPGA_VIRTEX2)
Virtex2_info (desc);
#else
/* just in case */
} else
switch (desc->family) {
case Xilinx_Spartan2:
-#if (CONFIG_FPGA & CFG_SPARTAN2)
+#if defined(CONFIG_FPGA_SPARTAN2)
ret_val = Spartan2_reloc (desc, reloc_offset);
#else
printf ("%s: No support for Spartan-II devices.\n",
#endif
break;
case Xilinx_Spartan3:
-#if (CONFIG_FPGA & CFG_SPARTAN3)
+#if defined(CONFIG_FPGA_SPARTAN3)
ret_val = Spartan3_reloc (desc, reloc_offset);
#else
printf ("%s: No support for Spartan-III devices.\n",
#endif
break;
case Xilinx_Virtex2:
-#if (CONFIG_FPGA & CFG_VIRTEX2)
+#if defined(CONFIG_FPGA_VIRTEX2)
ret_val = Virtex2_reloc (desc, reloc_offset);
#else
printf ("%s: No support for Virtex-II devices.\n",
return ret_val;
}
-#endif /* CONFIG_FPGA & CFG_FPGA_XILINX */
+#endif /* CONFIG_FPGA && CONFIG_FPGA_XILINX */
* Virtex2 FPGA configuration support
*/
#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA CFG_XILINX_VIRTEX2
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_VIRTEX2
#define CFG_FPGA_PROG_FEEDBACK
/* FPGA - Spartan 2 */
/* experiment
-#define CONFIG_FPGA CFG_SPARTAN3
+#define CONFIG_FPGA
+#define CONFIG_FPGA_XILINX
+#define CONFIG_FPGA_SPARTAN3
#define CONFIG_FPGA_COUNT 1
#define CFG_FPGA_PROG_FEEDBACK
#define CFG_FPGA_CHECK_CTRLC
/*-----------------------------------------------------------------------
* FPGA stuff
*-----------------------------------------------------------------------*/
-#define CONFIG_FPGA CFG_ALTERA_CYCLON2
+#define CONFIG_FPGA
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
#define CFG_FPGA_CHECK_CTRLC
#define CFG_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
*********************************************************************/
#define CFG_SPARTAN2 CFG_FPGA_DEV( 0x1 )
#define CFG_VIRTEX_E CFG_FPGA_DEV( 0x2 )
-#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
+#define CFG_VIRTEX2 CFG_FPGA_DEV( 0x4 )
#define CFG_SPARTAN3 CFG_FPGA_DEV( 0x8 )
#define CFG_XILINX_SPARTAN2 (CFG_FPGA_XILINX | CFG_SPARTAN2)
#define CFG_XILINX_VIRTEX_E (CFG_FPGA_XILINX | CFG_VIRTEX_E)
-#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
+#define CFG_XILINX_VIRTEX2 (CFG_FPGA_XILINX | CFG_VIRTEX2)
#define CFG_XILINX_SPARTAN3 (CFG_FPGA_XILINX | CFG_SPARTAN3)
/* XXX - Add new models here */