PXA: Fixup PXA25x boards after start.S update

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>

diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index 90c5bf897476a64c1397b1147fbb5bbfafb26495..07bc895f44ff1543c6e4ff93286db33a1f587eb8 100644 (file)
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -175,7 +175,7 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define        CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define        CONFIG_SYS_INIT_SP_ADDR         0xfffff800
 
 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
 

diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
index bdb5f57e429d9084b1697feeddc2dd865e9901cd..026e1831681b5a24bf7c2c51d9c6d14e18ec30bb 100644 (file)
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -157,7 +157,7 @@
 #define        CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define        CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define        CONFIG_SYS_INIT_SP_ADDR         0xfffff800
 
 /*
  * NOR FLASH

diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 620d270893e4338f94757d2347f2662e88102b8c..c208a25ca63571117f5dfa972e9e5e026af53099 100644 (file)
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -291,7 +291,7 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define        CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define        CONFIG_SYS_INIT_SP_ADDR         0xfffff800
 
 /*
  * GPIO settings

diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 6dce8aeaf1e0f0cf8f7d5037c2ee33e08dec3a34..5c59ac78aa0fe00d9c5f4d931208babbcfc638a3 100644 (file)
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -168,7 +168,7 @@
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define        CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define        CONFIG_SYS_INIT_SP_ADDR         0xfffff800
 
 /*
  * FLASH and environment organization