riscv: dts: jh7110: Add PLL clock controller node

Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 58e332e9d7189e00013ae4c764490c0e5905bc85..7a8141a8e9f0ce032f8631feeb64f86c1b3f52cc 100644 (file)
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -498,8 +498,14 @@
                };
 
                sys_syscon: sys_syscon@13030000 {
-                       compatible = "starfive,jh7110-sys-syscon","syscon";
+                       compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
                        reg = <0x0 0x13030000 0x0 0x1000>;
+
+                       pllclk: clock-controller {
+                               compatible = "starfive,jh7110-pll";
+                               clocks = <&osc>;
+                               #clock-cells = <1>;
+                       };
                };
 
                sysgpio: pinctrl@13040000 {