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ARM: at91: sama5d2: configure the L2 cache memory
authorSamuel Mescoff <samuel.mescoff@mobile-devices.fr>
Tue, 16 Feb 2016 08:45:06 +0000 (09:45 +0100)
committerAndreas Bießmann <andreas.devel@googlemail.com>
Thu, 18 Feb 2016 20:34:41 +0000 (21:34 +0100)
commitf7cf291aa788eb5b64c0d16de529b1a378f509bb
tree7fb741b4c492033d0b5fb364dc372dbb995898b9tree | snapshot
parentc21c28b6f39468dcc13f82458fa3c6f6c5dce9d9commit | diff
ARM: at91: sama5d2: configure the L2 cache memory

The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.

Based on the commit b5ea95ef2b5b from the at91bootstrap repository.

Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
arch/arm/mach-at91/atmel_sfr.c diff | blob | history
arch/arm/mach-at91/include/mach/at91_common.h diff | blob | history
arch/arm/mach-at91/include/mach/sama5_sfr.h diff | blob | history
arch/arm/mach-at91/spl_atmel.c diff | blob | history
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